4-Bit x 64-word FIFO register; 3-state
• Synchronous or asynchronous
• 3-state outputs
• 30 MHz (typical) shift-in and
• Readily expandable in word and bit
• Pinning arranged for easy board
layout: input pins directly opposite
• Output capability: driver (8 mA)
• ICC category: LSI.
• High-speed disc or tape controller
• Communications buffer.
The 74HC/HCT7403 are high-speed
Si-gate CMOS devices. They are
specified in compliance with JEDEC
The “7403” is an expandable, First-In
First-Out (FIFO) memory organized
as 64 words by 4 bits. A guaranteed
15 MHz data-rate makes it ideal for
high-speed applications. A higher
data-rate can be obtained in
applications where the status flags
are not used (burst-mode).
With separate controls for shift-in (SI)
and shift-out (SO), reading and
writing operations are completely
independent, allowing synchronous
and asynchronous data transfers.
Additional controls include a
master-reset input (MR), an output
enable input (OE) and flags. The
data-in-ready (DIR) and
data-out-ready (DOR) flags indicate
the status of the device.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
propagation delay SO,
SI to DIR and DOR
CL = 15 pF;
VCC = 5 V
15 17 ns
30 30 MHz
3.5 3.5 pF
475 490 pF
1. For HC the condition is VI = GND to VCC.
For HCT the condition is VI = GND to VCC −1.5 V.
PIN POSITION MATERIAL