Dual JK ﬂip-ﬂop
The HEF4027B is a dual JK flip-flop which is
edge-triggered and features independent set direct
(SD), clear direct (CD), clock (CP) inputs and outputs
(O,O). Data is accepted when CP is LOW, and transferred
to the output on the positive-going edge of the clock. The
active HIGH asynchronous clear-direct (CD) and set-direct
(SD) are independent and override the J, K, and CP inputs.
The outputs are buffered for best system performance.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
SD CD CP J
SD CD CP J K On + 1
On + 1
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going transition
On + 1 = state after clock positive transition
J,K synchronous inputs
CP clock input (L to H edge-triggered)
SD asynchronous set-direct input (active HIGH)
CD asynchronous clear-direct input (active HIGH)
O true output
O complement output
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
HEF4027BP(N): 16-lead DIL; plastic (SOT38-1)
HEF4027BD(F): 16-lead DIL; ceramic (cerdip) (SOT74)
HEF4027BT(D): 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
FAMILY DATA, IDD LIMITS category FLIP-FLOPS
See Family Specifications