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LatticeSemiconductor
LatticeSemiconductor


2096VL

2.5VIn-SystemProgrammableSuperFASTHighDensityPLD



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2096VL pdf
ispLSI® 2096VL
2.5V In-System Programmable
SuperFAST™ High Density PLD
Features
Functional Block Diagram
• SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC
— 4000 PLD Gates
— 96 I/O Pins, Six Dedicated Inputs
— 96 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functional, JEDEC and Pinout Compatible
with ispLSI 2096V and 2096VE Devices
• 2.5V LOW VOLTAGE 2096 ARCHITECTURE
— Interfaces with Standard 3.3V Devices (Inputs and
I/Os are 3.3V Tolerant)
— 85 mA Typical Active Current
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 165 MHz Maximum Operating Frequency
tpd = 5.5 ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— 2.5V In-System Programmability (ISP™) Using
Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of
Wired-OR or Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
• THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Output Routing Pool (ORP)
C7 C6 C5 C4
A0
DQ
A1 Logic D Q
A2 GLB Array D Q
DQ
A3
A4 A5 A6 A7
Output Routing Pool (ORP)
Output Routing Pool (ORP)
C3 C2 C1 C0
B7
Global Routing Pool
(GRP)
B6
B5
B4
B0 B1 B2 B3
Output Routing Pool (ORP)
Description
0919/2096VL
The ispLSI 2096VL is a High Density Programmable
Logic Device containing 96 Registers, six Dedicated
Input pins, three Dedicated Clock Input pins, two dedi-
cated Global OE input pins and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 2096VL fea-
tures in-system programmability through the Boundary
Scan Test Access Port (TAP) and is 100% IEEE 1149.1
Boundary Scan Testable. The ispLSI 2096VL offers non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 2096VL device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. C7 (see Figure 1). There are a total of 24 GLBs in the
ispLSI 2096VL device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
The devices also have 96 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control, and
the output drivers can source 4 mA or sink 8 mA. Each
output can be programmed independently for fast or slow
output slew rate to minimize overall output switching
Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
2096vl_02
1



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2096VL pdf
Specifications ispLSI 2096VL
Functional Block Diagram
Figure 1. ispLSI 2096VL Functional Block Diagram
Megablock
Generic Logic
Blocks (GLBs)
Input Bus
Output Routing Pool (ORP)
C7 C6 C5 C4
Input Bus
Output Routing Pool (ORP)
C3 C2 C1 C0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
TDI/IN 0
TMS/IN 1
RESET
BSCAN
A0
Global
A1 Routing
Pool
(GRP)
A2
A3
A4 A5 A6 A7
Output Routing Pool (ORP)
Input Bus
B0 B1 B2 B3
Output Routing Pool (ORP)
Input Bus
I/O 63
B7 I/O 62
I/O 61
I/O 60
I/O 59
B6 I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
B5 I/O 53
I/O 52
I/O 51
I/O 50
B4 I/O 49
I/O 48
0917/2096VL
noise. Device pins can be safely driven to 3.3V signal
levels to support mixed-voltage systems.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the two ORPs. Each
ispLSI 2096VL device contains three Megablocks.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2096VL are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration is a totem-pole
configuration. The open-drain/totem-pole option is se-
lectable through the ispDesignEXPERT software tools.
Clocks in the ispLSI 2096VL device are selected using
the dedicated clock pins. Three dedicated clock pins (Y0,
Y1, Y2) or an asynchronous clock can be selected on a
GLB basis. The asynchronous or Product Term clock can
be generated in any GLB for its own clock.
2



Part Number 2096VL
Description 2.5VIn-SystemProgrammableSuperFASTHighDensityPLD
Maker LatticeSemiconductor - LatticeSemiconductor
Total Page 11 Pages
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