http://www.www.datasheet4u.com

900,000+ Datasheet PDF Search and Download

Datasheet4U offers most rated semiconductors datasheets pdf




LatticeSemiconductor
LatticeSemiconductor


2064VL

2.5VIn-SystemProgrammableSuperFASTHighDensityPLD


No Preview Available !

2064VL pdf
ispLSI® 2064VL
2.5V In-System Programmable
SuperFAST™ High Density PLD
Features
• SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC
— 2000 PLD Gates
— 64 and 32 I/O Pin Versions, Four Dedicated Inputs
— 64 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functional, JEDEC and Pinout Compatible with
ispLSI 2064V and 2064VE Devices
• 2.5V LOW VOLTAGE 2064 ARCHITECTURE
— Interfaces with Standard 3.3V TTL Devices (Inputs
and I/Os are 3.3V Tolerant)
— 60 mA Typical Active Current
• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 165MHz Maximum Operating Frequency
tpd = 5.5ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— 2.5V In-System Programmability (ISP™) Using
Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of Wired-OR
or Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE
• THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Functional Block Diagram
Input Bus
Output Routing Pool (ORP)
B7 B6 B5 B4
A0
Global Routing Pool
(GRP)
B3
A1
A2 GLB
A3
DQ
Logic D Q
Array D Q
DQ
A4 A5 A6 A7
Output Routing Pool (ORP)
Input Bus
B2
B1
B0
Description
0139A/2064VL
The ispLSI 2064VL is a High Density Programmable
Logic Device available in 64 and 32 I/O-pin versions. The
device contains 64 Registers, four Dedicated Input pins,
three Dedicated Clock Input pins, two dedicated Global
OE input pins and a Global Routing Pool (GRP). The
GRP provides complete interconnectivity between all of
these elements. The ispLSI 2064VL features in-system
programmability through the Boundary Scan Test Ac-
cess Port (TAP) and is 100% IEEE 1149.1 Boundary
Scan Testable. The ispLSI 2064VL offers non-volatile
reprogrammability of the logic, as well as the intercon-
nect, to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 2064VL device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…B7 (see Figure 1). There are a total of 16 GLBs in the
ispLSI 2064VL device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
2064vl_02
1



No Preview Available !

2064VL pdf
Specifications ispLSI 2064VL
Functional Block Diagram
Figure 1. ispLSI 2064VL Functional Block Diagram (64-I/O and 32-I/O Versions)
Megablock
Input Bus
Output Routing Pool (ORP)
B7 B6 B5 B4
Generic Logic
Blocks (GLBs)
Megablock
Input Bus
Output Routing Pool (ORP)
B7 B6 B5 B4
Generic Logic
Blocks (GLBs)
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
TDI/IN 0
TMS/IN 1
RESET
BSCAN
A0
A1 Global Routing Pool
(GRP)
A2
A3
A4 A5 A6 A7
Output Routing Pool (ORP)
Input Bus
I/O 47
I/O 0
B3
I/O 46
I/O 1
I/O 45
I/O 2
I/O 44
I/O 3
I/O 43
I/O 42
B2 I/O 41
I/O 40
I/O 39
I/O 38
B1 I/O 37
I/O 36
I/O 35
I/O 4
I/O 34
I/O 5
B0
I/O 33
I/O 6
I/O 32
I/O 7
TCK/IN 3
TDO/IN 2
TDI/IN 0
TDO/IN 1
0139B/2064VL
BSCAN
A0
A1 Global Routing Pool
(GRP)
A2
A3
A4 A5 A6 A7
Output Routing Pool (ORP)
Input Bus
I/O 23
B3 I/O 22
I/O 21
I/O 20
B2
B1
I/O 19
I/O 18
B0 I/O 17
I/O 16
GOE0/IN 3
TMS/IN 2
0139B/2064VL.32IO
The 64-I/O 2064VL contains 64 I/O cells, while the 32-
I/O version contains 32 I/O cells. Each I/O cell is directly
connected to an I/O pin and can be individually pro-
grammed to be a combinatorial input, output or
bi-directional I/O pin with 3-state control and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
Device pins can be safely driven to 3.3V signal levels to
support mixed-voltage systems.
Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and
two or one ORPs are connected together to make a
Megablock (see Figure 1). The outputs of the eight GLBs
are connected to a set of 32 or 16 universal I/O cells by
two or one ORPs. Each ispLSI 2064VL device contains
two Megablocks.
GLB basis. The asynchronous or Product Term clock can
be generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2064VL are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration is totem-pole
configuration. The open-drain/totem-pole option is se-
lectable through the ispDesignEXPERT software tools.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2064VL device are selected using
the dedicated clock pins. Three dedicated clock pins (Y0,
Y1, Y2) or an asynchronous clock can be selected on a
2



Part Number 2064VL
Description 2.5VIn-SystemProgrammableSuperFASTHighDensityPLD
Maker LatticeSemiconductor - LatticeSemiconductor
Total Page 14 Pages
PDF Download
2064VL pdf
Download PDF File
2064VL pdf
View for Mobile




Featured Datasheets

Part Number Description Manufacturers PDF
2064 QUAD1.5ADARLINGTONSWITCHES 2064
AllegroMicroSystems
PDF
2064VE 3.3VIn-SystemProgrammableHighDensitySuperFASTPLD 2064VE
LatticeSemiconductor
PDF
2064VL 2.5VIn-SystemProgrammableSuperFASTHighDensityPLD 2064VL
LatticeSemiconductor
PDF


Part Number Start With

0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F  G  H  I  J  K  L  M  N  O  P  Q  R  S  T  U  V  W  X  Y  Z

site map

webmaste! click here

contact us

Buy Components