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IF Diversity Receiver
AD6649
FEATURES
APPLICATIONS
SNR = 73.0 dBFS in a 95 MHz bandwidth at
185 MHz AIN and 245.76 MSPS
SFDR = 85 dBc at 185 MHz AIN and 250 MSPS
Noise density = −151.2 dBFS/Hz input at 185 MHz, −1 dBFS
AIN and 250 MSPS
Total power consumption: 1 W with fixed-frequency NCO,
95 MHz FIR filter
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Integrated dual-channel ADC
Sample rates of up to 250 MSPS
IF sampling frequencies to 400 MHz
Internal ADC voltage reference
Flexible input range
1.4 V p-p to 2.1 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Integrated wideband digital processor
32-bit complex numerically controlled oscillator (NCO)
FIR filter with 2 modes
Real output from an fS/4 output NCO
Amplitude detect bits for efficient AGC implementation
Energy saving power-down modes
Decimated, interleaved real LVDS data outputs
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMax, WCDMA,
CDMA2000, GSM, EDGE, LTE
General-purpose software radios
Broadband data applications
GENERAL DESCRIPTION
The AD6649 is a mixed-signal intermediate frequency (IF) receiver
consisting of dual 14-bit, 250 MSPS ADCs and a wideband digital
downconverter (DDC). The AD6649 is designed to support
communications applications, where low cost, small size, wide
bandwidth, and versatility are desired.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations. A duty cycle stabilizer is provided to
compensate for variations in the ADC clock duty cycle, allowing
the converters to maintain excellent performance.
FUNCTIONAL BLOCK DIAGRAM
AVDD
FDA
DRVDD
VIN+A
VIN–A
THRESHOLD DETECT
ADC
DC
CORRECTION
I SELECTABLE
FIR
FILTER
Q SELECTABLE
FIR
FILTER
AD6649
DIGITAL
INTERLEAVING
OR+
OR–
D13+/D13–
D0+/D0–
REFERENCE
32-BIT
TUNING NCO
VIN–B
VIN+B
DC
CORRECTION
ADC
THRESHOLD DETECT
Q SELECTABLE
FIR
FILTER
I SELECTABLE
FIR
FILTER
fS/4
NCO
DIVIDE 1
TO 8
DUTY
CYCLE
STABILIZER
DCO
GENERATION
MULTICHIP
SYNC
PROGRAMMING DATA
SPI
CLK+
CLK–
DCO+
DCO–
SYNC
AGND
FDB
PDWN
OEB
SDIO SCLK CSB
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.


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AD6649
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
General Description ......................................................................... 1 
Functional Block Diagram .............................................................. 1 
Revision History ............................................................................... 2 
Product Highlights ........................................................................... 3 
Specifications..................................................................................... 4 
ADC DC Specifications................................................................. 4 
ADC AC Specifications ................................................................. 5 
Digital Specifications ..................................................................... 6 
Switching Specifications ................................................................ 8 
Timing Specifications .................................................................. 9 
Absolute Maximum Ratings.......................................................... 10 
Thermal Characteristics ............................................................ 10 
ESD Caution................................................................................ 10 
Pin Configuration and Function Descriptions........................... 11 
Typical Performance Characteristics ........................................... 13 
Equivalent Circuits ......................................................................... 16 
Theory of Operation ...................................................................... 17 
ADC Architecture ...................................................................... 17 
Analog Input Considerations.................................................... 17 
Voltage Reference ....................................................................... 19 
Clock Input Considerations ...................................................... 19 
Power Dissipation and Standby Mode..................................... 20 
Digital Outputs ........................................................................... 21 
Digital Processing ........................................................................... 22 
Numerically Controlled Oscillator (NCO) ............................. 22 
NCO and FIR Filter Modes....................................................... 22 
REVISION HISTORY
4/11—Revision 0: Initial Version
fS/4 Fixed-Frequency NCO ....................................................... 22 
Numerically Controlled Oscillator (NCO) ................................. 23 
Frequency Translation ............................................................... 23 
NCO Synchronization ............................................................... 23 
NCO Amplitude and Phase Dither.......................................... 23 
FIR Filters ........................................................................................ 24 
FIR Synchronization .................................................................. 24 
Filter Performance...................................................................... 24 
Output NCO ............................................................................... 25 
ADC Overrange and Gain Control.............................................. 26 
ADC Overrange (OR)................................................................ 26 
Gain Switching............................................................................ 26 
DC Correction ................................................................................ 27 
Channel/Chip Synchronization.................................................... 28 
Serial Port Interface (SPI).............................................................. 29 
Configuration Using the SPI..................................................... 29 
Hardware Interface..................................................................... 29 
SPI Accessible Features.............................................................. 30 
Memory Map .................................................................................. 31 
Reading the Memory Map Register Table............................... 31 
Memory Map Register Table..................................................... 32 
Memory Map Register Description ......................................... 36 
Applications Information .............................................................. 39 
Design Guidelines ...................................................................... 39 
Outline Dimensions ....................................................................... 40 
Ordering Guide .......................................................................... 40 
Rev. 0 | Page 2 of 40


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ADC data outputs are internally connected directly to the digital
downconverter (DDC) of the receiver. The digital receiver has
two channels and provides processing flexibility. Each receive
channel has four cascaded signal processing stages: a 32-bit
frequency translator (numerically controlled oscillator (NCO)),
an optional sample rate converter, a fixed FIR filter, and an fS/4
fixed-frequency NCO.
In addition to the receiver DDC, the AD6649 has several
functions that simplify the automatic gain control (AGC)
function in the system receiver. The programmable threshold
detector allows monitoring of the incoming signal power using
the fast detect output bits of the ADC. If the input signal level
exceeds the programmable threshold, the fast detect indicator goes
high. Because this threshold indicator has low latency, the user
can quickly turn down the system gain to avoid an overrange
condition at the ADC input.
After digital processing, data is routed directly to the 14-bit
output port. These outputs operate at ANSI or reduced swing
LVDS signal levels.
The AD6649 receiver digitizes a wide spectrum of IF frequencies.
Each receiver is designed for simultaneous reception of the main
channel and the diversity channel. This IF sampling architecture
AD6649
greatly reduces component cost and complexity compared with
traditional analog techniques or less integrated digital methods.
In diversity applications, the output data format is real due to
the final NCO, which shifts the output center frequency to fS/4.
Flexible power-down options allow significant power savings,
when desired.
Programming for setup and control is accomplished using a 3-pin
SPI-compatible serial interface.
The AD6649 is available in a 64-lead LFCSP and is specified over
the industrial temperature range of −40°C to +85°C. This
product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Integrated dual, 14-bit, 250 MSPS ADCs.
2. Integrated wideband filter and 32-bit complex NCO.
3. Fast overrange and threshold detect.
4. Proprietary differential input maintains excellent SNR
performance for input frequencies of up to 400 MHz.
5. SYNC input allows synchronization of multiple devices.
6. 3-pin, 1.8 V SPI port for register programming and register
readback.
Rev. 0 | Page 3 of 40


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AD6649
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input,1 1.75 V p-p full-scale input range,
duty cycle stabilizer (DCS) enabled, NCO enabled, FIR filter enabled, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
MATCHING CHARACTERISTIC
Offset Error
Gain Error
TEMPERATURE DRIFT
Offset Error
Gain Error
INPUT REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span
Input Capacitance2
Input Resistance3
Input Common-Mode Voltage
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD4
IDRVDD4 (Fixed-Frequency NCO, 95 MHz FIR Filter)
IDRVDD4 (Tunable-Frequency NCO, 100 MHz FIR Filter)
POWER CONSUMPTION
Sine Wave Input (Fixed-Frequency NCO, 95 MHz FIR Filter)
Sine Wave Input (Tunable-Frequency NCO, 100 MHz FIR Filter)
Standby Power5
Power-Down Power
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min Typ
14
Max
Guaranteed
±10
−5.5 +2.5
±13
±2.5
±15
±50
1.32
1.75
2.5
20
0.9
Unit
Bits
mV
%FSR
mV
%FSR
ppm/°C
ppm/°C
LSB rms
V p-p
pF
V
1.7 1.8 1.9
1.7 1.8 1.9
V
V
271 275
283 300
375
mA
mA
mA
997
1163
104
10
1035
mW
mW
mW
mW
1 A −1.0 dBFS input level at the analog inputs corresponds to an output level of −2.5 dBFS when using the fixed-frequency NCO and 95 MHz FIR filter. When using the
tunable-frequency NCO and 100 MHz FIR filter, the output level is −1.3 dBFS. These respective output level reductions are due to FIR filter losses. See the FIR Filters
section for more details.
2 Input capacitance refers to the effective capacitance between one differential input pin and AGND.
3 Input resistance refers to the effective resistance between one differential input pin and its complement.
4 Measured with a 185 MHz, full-scale sine wave input on both channels and an NCO frequency of 62.5 MHz (fS/4).
5 Standby power is measured with a dc input and the CLK pin inactive (set to AVDD or AGND).
Rev. 0 | Page 4 of 40


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AD6649
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input,1 1.75 V p-p full-scale input range,
DCS enabled, NCO enabled, FIR filter enabled, unless otherwise noted.
Table 2.
Parameter2
SIGNAL-TO-NOISE RATIO (SNR)3
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
WORST OTHER HARMONIC OR SPUR
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
TWO-TONE SFDR
fIN = 184.12 MHz, 187.12 MHz (−7 dBFS)
CROSSTALK4
ANALOG INPUT BANDWIDTH
Temperature
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
Full
25°C
Min Typ
74.5
74.2
73.9
73.4
70.9
72.9
73.4
73.0
72.3
71.7
68.7
71.0
−92
−88
−85
−85
−89
92
88
85
85
80
84
−95
−94
−93
−93
−84
88
95
1000
Max Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
dBc
dBc
dBc
−80 dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
−80 dBc
dBc
dBc
dB
MHz
1 A −1.0 dBFS input level at the analog inputs corresponds to an output level of −2.5 dBFS when using the fixed-frequency NCO and 95 MHz FIR filter. When using the
tunable-frequency NCO and 100 MHz FIR filter, the output level is −1.3 dBFS. These respective output level reductions are due to FIR filter losses. See the FIR Filters
section for more details.
2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
3 SNR specifications are for filtered 95 MHz bandwidth.
4 Crosstalk is measured at 100 MHz with −1 dBFS on one channel and with no input on the alternate channel.
Rev. 0 | Page 5 of 40


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AD6649
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input,1 1.0 V internal reference,
DCS enabled, unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
SYNC INPUT
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
LOGIC INPUT (CSB)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (SCLK)3
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT/OUTPUT (SDIO)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (OEB, PDWN)3
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Temperature Min
Typ Max
CMOS/LVDS/LVPECL
Full 0.9
Full 0.3
3.6
Full AGND
AVDD
Full 0.9
1.4
Full +10
+22
Full −22
−10
Full 4
Full 8 10 12
CMOS/LVDS
Full 0.9
Full AGND
AVDD
Full 1.2
AVDD
Full AGND
0.6
Full −5
+5
Full −5
+5
Full 1
Full 12 16 20
Full 1.22
2.1
Full 0
0.6
Full −5
+5
Full −80
−45
Full 26
Full 2
Full 1.22
2.1
Full 0
0.6
Full 45
70
Full −5
+5
Full 26
Full 2
Full 1.22
2.1
Full 0
0.6
Full 45
70
Full −5
+5
Full 26
Full 5
Full 1.22
Full 0
Full 45
Full −5
2.1
0.6
70
+5
Unit
V
V p-p
V
V
μA
μA
pF
V
V
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
μA
μA
Rev. 0 | Page 6 of 40


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AD6649
Parameter
Input Resistance
Input Capacitance
DIGITAL OUTPUTS
FDA and FDB
High Level Output Voltage
IOH = 50 μA
IOH = 0.5 mA
Low Level Output Voltage
IOL = 1.6 mA
IOL = 50 μA
LVDS Data and OR Outputs
Differential Output Voltage (VOD), ANSI Mode
Output Offset Voltage (VOS),
ANSI Mode
Differential Output Voltage (VOD), Reduced Swing Mode
Output Offset Voltage (VOS),
Reduced Swing Mode
Temperature Min
Full
Full
Typ Max
26
5
Unit
pF
Full 1.79
Full 1.75
V
V
Full 0.2 V
Full 0.05 V
Full 250 350 450 mV
Full 1.15 1.25 1.35 V
Full 150 200 280 mV
Full 1.15 1.25 1.35 V
1 A −1.0 dBFS input level at the analog inputs corresponds to an output level of −2.5 dBFS when using the fixed-frequency NCO and 95 MHz FIR filter. When using the
tunable-frequency NCO and 100 MHz FIR filter, the output level is −1.3 dBFS. These respective output level reductions are due to FIR filter losses. See the FIR Filters
section for more details.
2 Pull-up.
3 Pull-down.
Rev. 0 | Page 7 of 40


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AD6649
SWITCHING SPECIFICATIONS
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate1
CLK Period—Divide-by-1 Mode (tCLK)
CLK Pulse Width High (tCH)
Divide-by-1 Mode, DCS Enabled
Divide-by-1 Mode, DCS Disabled
Divide-by-3 Through Divide-by-8 Modes, DCS Enabled
DATA OUTPUT PARAMETERS (DATA, OR)
Data Propagation Delay (tPD)
DCO Propagation Delay (tDCO)
DCO-to-Data Skew (tSKEW)
Pipeline Delay—Fixed-Frequency NCO, 95 MHz FIR Filter (Latency)
Pipeline Delay—Tunable-Frequency NCO, 100 MHz FIR Filter (Latency)
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Wake-Up Time (from Standby)
Wake-Up Time (from Power-Down)
OUT-OF-RANGE RECOVERY TIME
1 Conversion rate is the clock rate after the divider.
Temperature Min Typ Max Unit
Full
Full 40
Full 4.0
625 MHz
250 MSPS
ns
Full
1.8 2.0 2.2
ns
Full
1.9 2.0 2.1
ns
Full 0.8
ns
Full 4.8 ns
Full 5.5 ns
Full
0.1 0.7 1.3
ns
Full 23 Cycles
Full 43 Cycles
Full 1.0 ns
Full 0.1 ps rms
Full 10 μs
Full 250 μs
Full 3 Cycles
Rev. 0 | Page 8 of 40


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AD6649
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
tSSYNC
tHSYNC
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
Conditions
Min Typ Max Unit
SYNC to the rising edge of CLK setup time
SYNC to the rising edge of CLK hold time
0.3 ns
0.4 ns
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Time required for the SDIO pin to switch from an input to an output
relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to an input
relative to the SCLK rising edge
2
2
40
2
2
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
Timing Diagrams
CLK+
CLK–
DCO+
DCO–
D0+ TO D13+
D0– TO D13–
CHA0
tCH
tPD
CHB0 CHA1
tCLK
tDCO
tSKEW
CHB1 CHA2 CHB2 CHA3 CHB3 CHA4 CHB4
Figure 2. Interleaved LVDS Mode Data Output Timing
CHA5
CHB5
CHA6
CHB6
CLK+
SYNC
tSSYNC
tHSYNC
Figure 3. SYNC Timing Inputs
Rev. 0 | Page 9 of 40


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AD6649
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
Electrical
AVDD to AGND
DRVDD to AGND
VIN+A/VIN+B, VIN−A/VIN−B to AGND
CLK+, CLK− to AGND
SYNC to AGND
VCM to AGND
CSB to AGND
SCLK to AGND
SDIO to AGND
OEB to AGND
PDWN to AGND
D0−/D0+ through D13−/D13+
to AGND
FDA/FDB to AGND
OR+/OR− to AGND
DCO+/DCO− to AGND
Environmental
Operating Temperature Range
(Ambient)
Maximum Junction Temperature
Under Bias
Storage Temperature Range
(Ambient)
Rating
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−40°C to +85°C
150°C
−65°C to +125°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the
customer board increases the reliability of the solder joints,
maximizing the thermal capability of the package.
Table 7. Thermal Resistance
Package
Type
Airflow
Velocity
(m/sec)
64-Lead LFCSP
9 mm × 9 mm
(CP-64-4)
0
1.0
2.0
θJA1, 2
26.8
21.6
20.2
θJC1, 3
1.14
θJB1, 4
10.4
Unit
°C/W
°C/W
°C/W
1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3 Per MIL-Std 883, Method 1012.1.
4 Per JEDEC JESD51-8 (still air).
Typical θJA is specified for a 4-layer PCB with solid ground
plane. As shown in Table 7, airflow increases heat dissipation,
which reduces θJA. In addition, metal in direct contact with the
package leads from metal traces, through holes, ground, and
power planes, reduces the θJA.
ESD CAUTION
Rev. 0 | Page 10 of 40


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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
CLK+ 1
CLK– 2
SYNC 3
FDA 4
FDB 5
DNC 6
DNC 7
D0– (LSB) 8
D0+ (LSB) 9
DRVDD 10
D1– 11
D1+ 12
D2– 13
D2+ 14
D3– 15
D3+ 16
AD6649
TOP VIEW
(Not to Scale)
48 PDWN
47 OEB
46 CSB
45 SCLK
44 SDIO
43 OR+
42 OR–
41 D13+ (MSB)
40 D13– (MSB)
39 D12+
38 D21–
37 DRVDD
36 D11+
35 D11–
34 D10+
33 D10–
AD6649
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG
GROUND FOR THE PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
Figure 4. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)
Table 8. Pin Function Descriptions (Interleaved Parallel LVDS Mode)
Pin No.
Mnemonic
Type
Description
ADC Power Supplies
10, 19, 28, 37
DRVDD
Supply
Digital Output Driver Supply (1.8 V Nominal).
49, 50, 53, 54, 59, 60, 63, 64
AVDD
Supply
Analog Power Supply (1.8 V Nominal).
6, 7, 55, 56, 58
DNC
Do Not Connect. Do not connect to this pin.
0
AGND,
Ground
Analog Ground. The exposed thermal paddle on the bottom of the
Exposed Paddle
package provides the analog ground for the part. This exposed
paddle must be connected to ground for proper operation.
ADC Analog
51
VIN+A
Input
Differential Analog Input Pin (+) for Channel A.
52
VIN−A
Input
Differential Analog Input Pin (−) for Channel A.
62
VIN+B
Input
Differential Analog Input Pin (+) for Channel B.
61
VIN−B
Input
Differential Analog Input Pin (−) for Channel B.
57
VCM
Output
Common-Mode Level Bias Output for Analog Inputs. This pin
should be decoupled to ground using a 0.1 μF capacitor.
1
CLK+
Input
ADC Clock Input—True.
2
CLK−
Input
ADC Clock Input—Complement.
ADC Fast Detect Outputs
4
FDA
Output
Channel A Fast Detect Indicator (CMOS Levels).
5
FDB
Output
Channel B Fast Detect Indicator (CMOS Levels).
Digital Input
3
SYNC
Input
Digital Synchronization Pin. Slave mode only.
Digital Outputs
9
D0+ (LSB)
Output
Channel A/Channel B LVDS Output Data 0—True.
8
D0− (LSB)
Output
Channel A/Channel B LVDS Output Data 0—Complement.
12
D1+
Output
Channel A/Channel B LVDS Output Data 1—True.
11
D1−
Output
Channel A/Channel B LVDS Output Data 1—Complement.
14
D2+
Output
Channel A/Channel B LVDS Output Data 2—True.
13
D2−
Output
Channel A/Channel B LVDS Output Data 2—Complement.
16
D3+
Output
Channel A/Channel B LVDS Output Data 3—True.
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AD6649
Pin No.
15
18
17
21
20
23
22
27
26
30
29
32
31
34
33
36
35
39
38
41
40
43
42
25
24
SPI Control
45
44
46
Output Enable and Power-Down
47
48
Mnemonic
D3−
D4+
D4−
D5+
D5−
D6+
D6−
D7+
D7−
D8+
D8−
D9+
D9−
D10+
D10−
D11+
D11−
D12+
D12−
D13+ (MSB)
D13− (MSB)
OR+
OR−
DCO+
DCO−
SCLK
SDIO
CSB
OEB
PDWN
Type
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Description
Channel A/Channel B LVDS Output Data 3—Complement.
Channel A/Channel B LVDS Output Data 4—True.
Channel A/Channel B LVDS Output Data 4—Complement.
Channel A/Channel B LVDS Output Data 5—True.
Channel A/Channel B LVDS Output Data 5—Complement.
Channel A/Channel B LVDS Output Data 6—True.
Channel A/Channel B LVDS Output Data 6—Complement.
Channel A/Channel B LVDS Output Data 7—True.
Channel A/Channel B LVDS Output Data 7—Complement.
Channel A/Channel B LVDS Output Data 8—True.
Channel A/Channel B LVDS Output Data 8—Complement.
Channel A/Channel B LVDS Output Data 9—True.
Channel A/Channel B LVDS Output Data 9—Complement.
Channel A/Channel B LVDS Output Data 10—True.
Channel A/Channel B LVDS Output Data 10—Complement.
Channel A/Channel B LVDS Output Data 11—True.
Channel A/Channel B LVDS Output Data 11—Complement.
Channel A/Channel B LVDS Output Data 12—True.
Channel A/Channel B LVDS Output Data 12—Complement.
Channel A/Channel B LVDS Output Data 13—True.
Channel A/Channel B LVDS Output Data 13—Complement.
Channel A/Channel B LVDS Overrange—True.
Channel A/Channel B LVDS Overrange—Complement.
Channel A/Channel B LVDS Data Clock Output—True.
Channel A/Channel B LVDS Data Clock Output—Complement.
Input
Input/Output
Input
SPI Serial Clock.
SPI Serial Data Input/Output.
SPI Chip Select (Active Low).
Input/Output
Input/Output
Output Enable Input (Active Low).
Power-Down Input (Active High). The operation of this pin
depends on the SPI mode and can be configured as power-down
or standby (see Table 14).
Rev. 0 | Page 12 of 40


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AD6649
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = 250 MSPS, DCS enabled, 1.75 V p-p differential input, VIN = −1.0 dBFS, 32k sample,
TA = 25°C, fixed-frequency NCO, 95 MHz BW FIR filter, unless otherwise noted. In the FFT plots that follow, the location of the second
and third harmonics is noted when they fall in the pass band of the filter. A −1.0 dBFS input level at the analog inputs corresponds to an
output level of −2.5 dBFS when using the fixed-frequency NCO and 95 MHz FIR filter. When using the tunable-frequency NCO and
100 MHz FIR filter, the output level is −1.3 dBFS. These respective output level reductions are due to FIR filter losses. See the FIR Filters
section for more details.
00
–20
ffSIN==23500.M1MSHPzS@ –1.0dBFS
SNR = 72dB (74.5dBFS)
fS = 250MSPS
–20
fIN = 185.1MHz @ –1.0dBFS
SNR = 70.5dB (73.0dBFS)
SFDR = 92dBc (IN-BAND)
SFDR = 84.5dBc (IN-BAND)
–40 –40
–60
–80
–100
SECOND HARMONIC
THIRD HARMONIC
–60
–80
–100
THIRD HARMONIC
–120
–120
–140
0
10 20 30 40 50 60 70 80 90 100 110 120
FREQUENCY (MHz)
Figure 5. AD6649 Single-Tone FFT with fIN = 30.1 MHz
0
ffSIN==29500.M1MSHPzS@ –1.0dBFS
–20 SNR = 71.6dB (74.1dBFS)
SFDR = 87.5dBc (IN-BAND)
–40
–140
0 10 20 30 40 50 60 70 80 90 100 110 120
FREQUENCY (MHz)
Figure 8. AD6649 Single-Tone FFT with fIN = 185.1 MHz
0
ffSIN==225200M.1SMPHSz @ –1.0dBFS
–20 SNR = 69.8dB (72.3dBFS)
SFDR = 84dBc (IN-BAND)
–40
–60
–80
–100
THIRD HARMONIC
SECOND HARMONIC
–60
–80
–100
SECOND HARMONIC
THIRD HARMONIC
–120
–120
–140
0
10 20 30 40 50 60 70 80 90 100 110 120
FREQUENCY (MHz)
Figure 6. AD6649 Single-Tone FFT with fIN = 90.1 MHz
0
–20
ffSIN==215400M.1SMPHSz @ –1.0dBFS
SNR = 71.1dB (73.6dBFS)
SFDR = 85dBc (IN-BAND)
–40
–140
0 10 20 30 40 50 60 70 80 90 100 110 120
FREQUENCY (MHz)
Figure 9. AD6649 Single-Tone FFT with fIN = 220.1 MHz
0
ffSIN==235005M.1SMPHSz @ –1.0dBFS
–20 SNR = 68.5dB (71.0dBFS)
SFDR = 83.5dBc (IN-BAND)
–40
–60
–80
–100
SECOND HARMONIC
THIRD HARMONIC
–60
–80
–100
SECOND HARMONIC
THIRD HARMONIC
–120
–120
–140
0
10 20 30 40 50 60 70 80 90 100 110 120
FREQUENCY (MHz)
Figure 7. AD6649 Single-Tone FFT with fIN = 140.1 MHz
–140
0 10 20 30 40 50 60 70 80 90 100 110 120
FREQUENCY (MHz)
Figure 10. AD6649 Single-Tone FFT with fIN = 305.1 MHz
Rev. 0 | Page 13 of 40


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AD6649
120
SFDR (dBFS)
100
80 SNR (dBFS)
60
40
SFDR (dBc)
20
SNR (dBc)
0
INPUT AMPLITUDE (dBFS)
Figure 11. AD6649 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 90.1 MHz
100
95
SFDR (dBc)
90
85
80
75 SNR (dBFS)
70
65
50
100 150 200 250 300 350 400 450
INPUT FREQUENCY (MHz)
Figure 12. AD6649 Single-Tone SNR/SFDR vs. Input Frequency (fIN)
0
–20
SFDR (dBc)
–40
IMD3 (dBc)
–60
–80
–100
SFDR (dBFS)
–120
–90.0
IMD3 (dBFS)
–78.5
–67.0 –55.5 –44.0 –32.5
INPUT AMPLITUDE (dBFS)
–21.0
–9.5
Figure 13. AD6649 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz, fS = 250 MSPS
0
–20
SFDR (dBc)
–40
IMD3 (dBc)
–60
–80
–100
SFDR (dBFS)
–120
–90.0
IMD3 (dBFS)
–78.5
–67.0 –55.5 –44.0 –32.5
INPUT AMPLITUDE (dBFS)
–21.0
–9.5
Figure 14. AD6649 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz, fS = 250 MSPS
0
250MSPS
–20
89.12MHz @ –7.0dBFS
92.12MHz @ –7.0dBFS
SFDR = 88dBc (96.5dBFS)
–40
–60
–80
–100
–120
–140
0
10 20 30 40 50 60 70 80 90 100 110 120
FREQUENCY (MHz)
Figure 15. AD6649 Two-Tone FFT with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz,
fS = 250 MSPS
0
250MSPS
–20
184.12MHz @ –7.0dBFS
187.12MHz @ –7.0dBFS
SFDR = 85dBc (93.5dBFS)
–40
–60
–80
–100
–120
–140
0
10 20 30 40 50 60 70 80 90 100 110 120
FREQUENCY (MHz)
Figure 16. AD6649 Two-Tone FFT with fIN1 = 184.12 MHz,
fIN2 = 187.12 MHz, fS = 250 MSPS
Rev. 0 | Page 14 of 40


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100
95
90
85
SFDR CHANNEL A (dBc)
SFDR CHANNEL B (dBc)
SNR CHANNEL A (dBFS)
SNR CHANNEL B (dBFS)
80
75
70
SAMPLE RATE (MSPS)
Figure 17. AD6649 Single-Tone SNR/SFDR vs. Sample Rate (fS) with
fIN = 90.1 MHz
AD6649
6000
5000
1.32 LSB rms
16,378 TOTAL HITS
4000
3000
2000
1000
0
OUTPUT CODE
Figure 18. AD6649 Grounded Input Histogram
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AD6649
EQUIVALENT CIRCUITS
AVDD
VIN
Figure 19. Equivalent Analog Input Circuit
AVDD
CLK+
AVDD
0.9V
15k
15k
AVDD
CLK–
Figure 20. Equivalent Clock Input Circuit
DRVDD
V+
DATAOUT–
V–
V–
DATAOUT+
V+
Figure 21. Equivalent LVDS Output Circuit
DRVDD
SDIO
350
26k
Figure 22. Equivalent SDIO Circuit
SCLK
OR
PDWN
350
26k
Figure 23. Equivalent SCLK or PDWN Input Circuit
CSB
AVDD
26k
350
Figure 24. Equivalent CSB Input Circuit
AVDD
AVDD
SYNC
16k
0.9V
0.9V
Figure 25. Equivalent SYNC Input Circuit
Rev. 0 | Page 16 of 40


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THEORY OF OPERATION
The AD6649 has two analog input channels, two filter channels,
and two digital output channels. The intermediate frequency
(IF) input signal passes through several stages before appearing
at the output port(s) as a filtered and optionally decimated
digital signal.
The dual ADC design can be used for diversity reception of signals,
where the ADCs operate identically on the same carrier but from
two separate antennae. The ADCs can also be operated with
independent analog inputs. The user can sample frequencies
from dc to 300 MHz using appropriate low-pass or band-pass
filtering at the ADC inputs with little loss in ADC performance.
Operation to 400 MHz analog input is permitted but occurs at
the expense of increased ADC noise and distortion.
Synchronization capability is provided to allow synchronized
timing between multiple devices.
Programming and control of the AD6649 are accomplished
using a 3-pin SPI-compatible serial interface.
ADC ARCHITECTURE
The AD6649 architecture consists of a dual front-end sample-
and-hold circuit, followed by a pipelined switched-capacitor
ADC. The quantized outputs from each stage are combined into
a final 14-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate on a new input
sample and the remaining stages to operate on the preceding
samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor digital-
to-analog converter (DAC) and an interstage residue amplifier
(MDAC). The MDAC magnifies the difference between the recon-
structed DAC output and the flash input for the next stage in
the pipeline. One bit of redundancy is used in each stage to
facilitate digital correction of flash errors. The last stage simply
consists of a flash ADC.
The input stage of each channel contains a differential sampling
circuit that can be ac- or dc-coupled in differential or single-
ended modes. The output staging block aligns the data, corrects
errors, and passes the data to the output buffers. The output buffers
are powered from a separate supply, allowing digital output noise to
be separated from the analog core. During power-down, the
output buffers go into a high impedance state.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD6649 is a differential switched-
capacitor circuit that has been designed for optimum performance
while processing a differential input signal.
The clock signal alternatively switches the input between sample
mode and hold mode (see the configuration shown in Figure 26).
When the input is switched into sample mode, the signal source
AD6649
must be capable of charging the sampling capacitors and settling
within 1/2 clock cycle.
A small resistor in series with each input can help reduce the
peak transient current required from the output stage of the
driving source. A shunt capacitor can be placed across the
inputs to provide dynamic charging currents. This passive
network creates a low-pass filter at the ADC input; therefore,
the precise values are dependent on the application.
In intermediate frequency (IF) undersampling applications, the
shunt capacitors should be reduced. In combination with the
driving source impedance, the shunt capacitors limit the input
bandwidth. Refer to the AN-742 Application Note, Frequency
Domain Response of Switched-Capacitor ADCs; the AN-827
Application Note, A Resonant Approach to Interfacing Amplifiers to
Switched-Capacitor ADCs; and the Analog Dialogue article,
“Transformer-Coupled Front-End for Wideband A/D Converters,”
for more information on this subject.
BIAS
VIN+
CPAR1
S
CS
CPAR2
S
CFB
HS
S
VIN–
CPAR1
CS
CPAR2
S
BIAS
S
CFB
Figure 26. Switched-Capacitor Input
For best dynamic performance, the source impedances driving
VIN+ and VIN− should be matched, and the inputs should be
differentially balanced.
Input Common Mode
The analog inputs of the AD6649 are not internally dc biased.
In ac-coupled applications, the user must provide this bias
externally. Setting the device so that VCM = 0.5 × AVDD (or
0.9 V) is recommended for optimum performance. An on-board
common-mode voltage reference is included in the design and is
available from the VCM pin. Using the VCM output to set the
input common mode is recommended. Optimum performance
is achieved when the common-mode voltage of the analog input
is set by the VCM pin voltage (typically 0.5 × AVDD). The
VCM pin must be decoupled to ground by a 0.1 μF capacitor, as
described in the Applications Information section. This
decoupling capacitor should be placed close to the pin to
minimize the series resistance and inductance between the part
and this capacitor.
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AD6649
Differential Input Configurations
Optimum performance is achieved while driving the AD6649
in a differential input configuration. For baseband applications,
the AD8138, ADA4937-2, ADA4938-2, and ADA4930-2
differential drivers provide excellent performance and a flexible
interface to the ADC.
The output common-mode voltage of the ADA4930-2 is easily
set with the VCM pin of the AD6649 (see Figure 27), and the
driver can be configured in a Sallen-Key filter topology to
provide band-limiting of the input signal.
15pF
VIN 76.8
0.1µF
90
120
200
33
5pF
ADA4930-2
33
200
15pF
15
VIN–
ADC
15VIN+ VCM
33
0.1µF
Figure 27. Differential Input Configuration Using the ADA4930-2
For baseband applications where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 28. To bias the
analog input, the VCM voltage can be connected to the center
tap of the secondary winding of the transformer.
2V p-p
49.9
0.1µF
C2
R3
R1
C1
R1
R3
C2
R2
VIN+
ADC
R2
33
VIN–
VCM
0.1µF
Figure 28. Differential Transformer-Coupled Configuration
The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few megahertz. Excessive signal power can also cause
core saturation, which leads to distortion.
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD6649. For applications where
SNR is a key parameter, differential double balun coupling is
the recommended input configuration (see Figure 30). In this
configuration, the input is ac-coupled and the CML is provided
to each input through a 33 Ω resistor. These resistors compensate
for losses in the input baluns to provide a 50 Ω impedance to
the driver.
In the double balun and transformer configurations, the value of
the input capacitors and resistors is dependent on the input fre-
quency and source impedance. Based on these parameters the
value of the input resistors and capacitors may need to be
adjusted or some components may need to be removed. Table 9
displays recommended values to set the RC network for different
input frequency ranges. However, these values are dependent on
the input signal and bandwidth and should be used only as a
starting guide. Note that the values given in Table 9 are for each
R1, R2, C2, and R3 component shown in Figure 28 and Figure 30.
Table 9. Example RC Network
Frequency R1
Range
Series
(MHz)
(Ω)
C1
Differential
(pF)
0 to 100 33
8.2
100 to 250 15
3.9
R2
Series
(Ω)
0
0
C2
Shunt
(pF)
15
8.2
R3
Shunt
(Ω)
49.9
49.9
An alternative to using a transformer-coupled input at frequencies
in the second Nyquist zone is to use an amplifier with variable
gain. The AD8375 or AD8376 digital variable gain amplifier
(DVGAs) provides good performance for driving the AD6649.
Figure 29 shows an example of the AD8376 driving the AD6649
through a band-pass antialiasing filter.
1000pF 180nH 220nH
1µH
AD8376
1µH
VPOS
301
1nF
165
5.1pF 3.9pF
165
15pF
VCM
1nF
2.5kΩ║2pF
68nH AD6649
1000pF 180nH 220nH
NOTES
1. ALL INDUCTORS ARE COILCRAFT® 0603CS COMPONENTS
WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (COILCRAFT 0603LS).
2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER
CENTERED AT 140MHz.
Figure 29. Differential Input Configuration Using the AD8376
2V p-p
0.1µF
PA
SS
0.1µF
P
0.1µF
33
33
C2
R3
R1
R2
VIN+
0.1µF
C1
R1
R3
C2
ADC
R2
VIN–
33
VCM
0.1µF
Figure 30. Differential Double Balun Input Configuration
Rev. 0 | Page 18 of 40


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VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD6649.
The full-scale input range can be adjusted by varying the reference
voltage via SPI. The input span of the ADC tracks reference voltage
changes linearly.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD6649 sample clock inputs,
CLK+ and CLK−, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or via capacitors. These pins are biased
internally (see Figure 31) and require no external bias. If the
inputs are floated, the CLK− pin is pulled low to prevent spurious
clocking.
AVDD
CLK+
4pF
0.9V
CLK–
4pF
Figure 31. Simplified Equivalent Clock Input Circuit
Clock Input Options
The AD6649 has a very flexible clock input structure. Clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter
is of the most concern, as described in the Jitter Considerations
section.
Figure 32 and Figure 33 show two preferable methods for clocking
the AD6649 (at clock rates of up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using an RF balun or RF transformer.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer is recom-
mended for clock frequencies from 10 MHz to 200 MHz. The
back-to-back Schottky diodes across the transformer secondary
limit clock excursions into the AD6649 to approximately 0.8 V p-p
differential. This limit helps prevent the large voltage swings of
the clock from feeding through to other portions of the AD6649
while preserving the fast rise and fall times of the signal, which
are critical to low jitter performance.
CLOCK
INPUT
390pF
Mini-Circuits®
ADT1-1WT, 1:1Z
XFMR 390pF
50100
390pF
SCHOTTKY
DIODES:
HSMS2822
ADC
CLK+
CLK–
Figure 32. Transformer-Coupled Differential Clock (Up to 200 MHz)
AD6649
CLOCK
INPUT
390pF
25
390pF
390pF
SCHOTTKY
25DIODES:
HSMS2822
ADC
CLK+
CLK–
Figure 33. Balun-Coupled Differential Clock (Up to 625 MHz)
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input pins
as shown in Figure 34. The AD9510, AD9511, AD9512, AD9513,
AD9514, AD9515, AD9516, AD9517, AD9518, AD9520, AD9522,
AD9523, AD9524, and ADCLK905/ADCLK907/ADCLK925 clock
drivers offer excellent jitter performance.
CLOCK
INPUT
CLOCK
INPUT
50k
0.1µF
AD95xx
0.1µF PECL DRIVER
50k
240
0.1µF
0.1µF
240
CLK+
100
ADC
CLK–
Figure 34. Differential PECL Sample Clock (Up to 625 MHz)
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 35. The AD9510,
AD9511, AD9512, AD9513, AD9514, AD9515, AD9516, AD9517,
AD9518, AD9520, AD9522, AD9523, and AD9524 clock drivers
offer excellent jitter performance.
CLOCK
INPUT
CLOCK
INPUT
50k
0.1µF
AD95xx
0.1µF LVDS DRIVER
50k
0.1µF
100
0.1µF
CLK+
ADC
CLK–
Figure 35. Differential LVDS Sample Clock (Up to 625 MHz)
Input Clock Divider
The AD6649 contains an input clock divider with the ability to
divide the input clock by integer values between 1 and 8. The
duty cycle stabilizer (DCS) is enabled by default on power-up.
The AD6649 clock divider can be synchronized using the external
SYNC input. Bit 1 and Bit 2 of Register 0x3A allow the clock
divider to be resynchronized on every SYNC signal or only on
the first SYNC signal after the register is written. A valid SYNC
causes the clock divider to reset to its initial state. This synchro-
nization feature allows multiple parts to have their clock dividers
aligned to guarantee simultaneous input sampling.
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AD6649
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensitive to
clock duty cycle. Commonly, a ±5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics.
The AD6649 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
the performance of the AD6649.
Jitter on the rising edge of the input clock is still of paramount
concern and is not reduced by the duty cycle stabilizer. The duty
cycle control loop does not function for clock rates less than
40 MHz nominally. The loop has a time constant associated
with it that must be considered when the clock rate can change
dynamically. A wait time of 1.5 μs to 5 μs is required after a
dynamic clock frequency increase or decrease before the DCS
loop is relocked to the input signal. During the time period that
the loop is not locked, the DCS loop is bypassed, and internal
device timing is dependent on the duty cycle of the input clock
signal. In such applications, it may be appropriate to disable the
duty cycle stabilizer. In all other applications, enabling the DCS
circuit is recommended to maximize ac performance.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input
frequency (fIN) due to jitter (tJ) can be calculated by
SNRHF = −10 log[(2π × fIN × tJRMS)2 + 10 (SNRLF /10) ]
In the equation, the rms aperture jitter represents the root-
mean-square of all jitter sources, which include the clock input,
the analog input signal, and the ADC aperture jitter specification.
IF undersampling applications are particularly sensitive to jitter,
as shown in Figure 36.
80
75
70
65
0.05ps
0.20ps
0.50ps
1.00ps
60
1.50ps
MEASURED
55
50
1
10 100
INPUT FREQUENCY (MHz)
1000
Figure 36. SNR (95 MHz BW) vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD6649.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal controlled oscillators make
the best clock sources. If the clock is generated from another type
of source (by gating, dividing, or another method), it should be
retimed by the original clock at the last step.
Refer to the AN-501 Application Note, Aperture Uncertainty
and ADC System Performance, and the AN-756 Application
Note, Sampled Systems and the Effects of Clock Phase Noise and
Jitter, for more information about jitter performance as it relates
to ADCs.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 37, the power dissipated by the AD6649 is
proportional to its sample rate. The data in Figure 37 was taken
using the same operating conditions as those used for the Typical
Performance Characteristics.
1.0 0.5
0.9
0.8 0.4
0.7 TOTAL POWER
0.6
0.3
0.5
IAVDD
0.4
0.3 IDRVDD
0.2
0.1
0.2
0.1
00
40 60 80 100 120 140 160 180 200 220 250
ENCODE FREQUENCY (MSPS)
Figure 37. AD6649 Power and Current vs. Sample Rate
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the AD6649 is placed in power-down
mode. In this state, the ADC typically dissipates 10 mW. During
power-down, the output drivers are placed in a high impedance
state. Asserting the PDWN pin low returns the AD6649 to its
normal operating mode. Note that PDWN is referenced to the
digital output driver supply (DRVDD) and should not exceed
that supply voltage.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering
power-down mode and then must be recharged when returning
to normal operation. As a result, wake-up time is related to the
time spent in power-down mode, and shorter power-down
cycles result in proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map Register
Description section and the AN-877 Application Note, Interfacing
to High Speed ADCs via SPI, for additional details.
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DIGITAL OUTPUTS
The AD6649 output drivers can be configured for either ANSI
LVDS or reduced drive LVDS using a 1.8 V DRVDD supply.
As detailed in the AN-877 Application Note, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI
control.
Digital Output Enable Function (OEB)
The AD6649 has a flexible three-state ability for the digital
output pins. The three-state mode is enabled using the OEB pin
or through the SPI interface. If the OEB pin is low, the output
data drivers are enabled. If the OEB pin is high, the output data
drivers are placed in a high impedance state. This OEB function
is not intended for rapid access to the data bus. Note that OEB
is referenced to the digital output driver supply (DRVDD) and
should not exceed that supply voltage.
When using the SPI interface, the data and fast detect outputs of
each channel can be independently three-stated by using the
AD6649
output enable bar bit (Bit 4) in Register 0x14. Because the
output data is interleaved, if only one of the two channels is
disabled, the data of the remaining channel is repeated in both
the rising and falling output clock cycles.
Timing
The AD6649 provides latched data with a pipeline delay of 23 or 43
input sample clock cycles, depending on the mode of operation.
Data outputs are available one propagation delay (tPD) after the
rising edge of the clock signal.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD6649.
These transients can degrade converter dynamic performance.
The lowest typical conversion rate of the AD6649 is 40 MSPS. At
clock rates below 40 MSPS, dynamic performance may degrade.
Data Clock Output (DCO)
The AD6649 also provides data clock output (DCO) intended
for capturing the data in an external register. Figure 2 shows a
graphical timing diagram of the AD6649 output modes.
Table 10. Output Data Format
VIN+ − VIN−,
Input (V)
Input Span = 1.75 V p-p (V)
VIN+ − VIN–
<–0.875
VIN+ − VIN–
–0.875
VIN+ − VIN–
0
VIN+ − VIN–
+0.875
VIN+ − VIN–
>+0.875
Offset Binary Output Mode
00 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1111
Twos Complement Mode (Default)
10 0000 0000 0000
10 0000 0000 0000
00 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1111
OR
1
0
0
0
1
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AD6649
DIGITAL PROCESSING
The AD6649 includes a digital processing section that provides
filtering. This digital processing section includes a numerically
controlled oscillator (NCO), a selectable FIR filter (high perfor-
mance or low latency), and a second coarse NCO (fS/4 fixed
value) for output frequency translation (complex to real). These
blocks can be configured in several modes to implement a
signal processing function. Refer to Figure 1 for the functional
block diagram of the AD6649.
NUMERICALLY CONTROLLED OSCILLATOR (NCO)
Frequency translation is accomplished with an NCO shared
between the two channels. Amplitude and phase dither can be
enabled on chip to improve the noise and spurious performance of
the NCO.
Because the filtering prevents usage of part of the Nyquist
spectrum, a means is needed to translate the sampled input
spectrum into the usable range of the decimation filter. To
achieve this, a 32-bit, tuning, complex NCO is provided. This
NCO/mixer allows the input spectrum to be tuned to dc, where
it can be effectively filtered by the subsequent filter blocks to
prevent aliasing.
When using the low latency FIR, the NCO must be tuned to fS/4
(0x40000000). This prevents unwanted aliases from falling back
into the band of interest.
NCO AND FIR FILTER MODES
The NCO and FIR blocks can be used in two modes depending on
the bandwidth and latency requirement of the application. The two
modes of operation of these blocks are summarized in Table 11.
Table 11. Signal Path Modes
Mode
Fixed-Frequency NCO,
95 MHz FIR Filter
Tunable-Frequency NCO,
100 MHz FIR Filter
FIR
Low latency
(default)
High performance
Output
Bandwidth at
245.76 MSPS
95 MHz
99.5 MHz
Two fixed-coefficient FIR filters provide filtering capability. A
low latency FIR or a high performance FIR can be selected. It
removes the negative frequency images to avoid aliasing negative
frequencies for real outputs. Figure 38, Figure 39, and Figure 40
show the progression of a 95 MHz bandwidth signal through the
filter stages when using the fixed-frequency NCO and 95 MHz FIR
filter with a sample rate of 245.76 MSPS. The tunable-frequency
NCO can be used instead and operates in a similar fashion. In
these modes, the output is centered at 61.44 MHz, assuming a
245.76 MSPS sample rate.
fS/4 FIXED-FREQUENCY NCO
A fixed-frequency fS/4 NCO is provided to translate the filtered,
decimated signal from dc to fS/4 to allow a real output. The fS/4
NCO is required in all operation modes because complex
output from the part is not supported.
REAL ADC INPUT
–108.94 –61.44 –13.94 0 13.94
61.44 108.94 122.88
Figure 38. Example AD6649 Real 95 MHz Bandwidth Input Signal Centered at
61.44 MHz (fADC = 245.76 MHz)
COMPLEX ADC OUTPUT/NCO OUTPUT
–122.88 –75.38
–47.5
0 47.5
75.38
122.88
Figure 39. Example AD6649 95 MHz Bandwidth Input Signal Tuned to DC
Using the NCO (NCO Frequency = 61.44 MHz)
TUNED NCO OUTPUT
0 13.94
61.44 108.94 122.88
Figure 40. Example AD6649 95 MHz Bandwidth Output Signal Tuned to fS/4
(NCO Frequency = 61.44 MHz)
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AD6649
NUMERICALLY CONTROLLED OSCILLATOR (NCO)
FREQUENCY TRANSLATION
NCO SYNCHRONIZATION
This processing stage comprises a digital tuner consisting of
a 32-bit complex numerically controlled oscillator (NCO). The
NCO is always enabled. This NCO block accepts a real input
from the ADC stage and outputs a frequency translated
complex (I and Q) output.
The NCO frequency is programmed in Register 0x52 through
Register 0x55. These four 8-bit registers make up a 32-bit
unsigned frequency programming word. Frequencies between
−CLK/2 and +CLK/2 are represented using the following
frequency words:
0x80000000 represents a frequency given by −CLK/2.
0x00000000 represents dc (frequency = 0 Hz).
0x7FFFFFFF represents CLK/2 − CLK/232.
Use the following equation to calculate the NCO frequency:
NCO_FREQ = 232 × Mod( f , fCLK )
f CLK
where:
NCO_FREQ is a 32-bit twos complement number representing
the NCO frequency register.
f is the desired carrier frequency in hertz.
fCLK is the AD6649 ADC clock rate in hertz.
The AD6649 NCOs within a single part or across multiple parts
can be synchronized using the external SYNC input. Bit 0 and
Bit 1 of Register 0x58 allow the NCO to be resynchronized on
every SYNC signal or only on the first SYNC signal after the
register is written. A valid SYNC causes the NCO to restart at
the programmed phase offset value.
NCO AMPLITUDE AND PHASE DITHER
The NCO block contains amplitude and phase dither to improve
the spurious performance. Amplitude dither improves perfor-
mance by randomizing the amplitude quantization errors within
the angular-to-Cartesian conversion of the NCO. This option
reduces spurs at the expense of a slightly raised noise floor. With
amplitude dither enabled, the NCO has an SNR of greater than
93 dB and an SFDR of greater than 115 dB. With amplitude dither
disabled, the SNR is increased to greater than 96 dB at the cost
of SFDR performance, which is reduced to 100 dB. The NCO
amplitude and phase dither are recommended and can be enabled
by setting Bit 1 and Bit 2 in Register 0x51.
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AD6649
FIR FILTERS
The two FIR filters that can be used are either a 47-tap, high
performance, fixed-coefficient FIR filter or a 21-tap, low latency,
fixed-coefficient FIR filter. These filters are useful in providing
alias protection at the device output. The high performance FIR
is a simple sum-of-products FIR filter with 47 filter taps and
21-bit fixed coefficients. Note that this filter does not decimate.
The normalized coefficients used in the implementation and the
decimal equivalent value of the coefficients are listed in Table 12.
Table 12. High Performance FIR Filter Coefficients
Coefficient
Number
Normalized
Coefficient
Decimal Coefficient
(21-Bit)
C0, C46
−0.0001335
−140
C1, C45
−0.0009689
−1016
C2, C44
−0.0024185
−2536
C3, C43
−0.0019341
−2028
C4, C42
0.0023584
2473
C5, C41
0.0051260
5375
C6, C40
−0.0009680
−1015
C7, C39
−0.0086231
−9042
C8, C38
−0.0011368
−1192
C9, C37
0.0142097
14900
C10, C36
0.0064697
6784
C11, C35
−0.0207596
−21768
C12, C34
−0.0161047
−16887
C13, C33
0.0274601
28794
C14, C32
0.0310631
32572
C15, C31
−0.0348339
−36526
C16, C30
−0.0557785
−58488
C17, C29
0.0415993
43620
C18, C28
0.0986786
103472
C19, C27
−0.0463982
−48652
C20, C26
−0.1893501
−198548
C21, C25
0.0505829
53040
C22, C24
0.6113434
641040
C23
0.9171314
961682
FIR SYNCHRONIZATION
The AD6649 filters within a single part or across multiple parts can
be synchronized using the external SYNC input. The filters can
be configured to be resynchronized on every SYNC signal or only
on the first SYNC signal after the SPI control register is written.
A valid SYNC causes the FIR filter to restart at the programmed
decimation phase value. Bit 4 and Bit 5 of Register 0x58 allow
the FIR to be resynchronized on every SYNC signal or only on
the first SYNC signal after the register is written.
FILTER PERFORMANCE
When using the fixed-frequency NCO and a 95 MHz FIR filter,
the output rate is equal to the sample clock rate. The composite
response of this mode is shown in Figure 41. The detailed pass-
band response for this mode is shown in Figure 42. To place the
part in this mode, set SPI Register 0x50 to 0xB0. When operating
in this mode, the NCO must be placed at fS/4, and the low latency
NCO select bit (Bit 0) in Register 0x5A must be set. It is important
to note that a −1.0 dBFS input level at the analog inputs corresponds
to an output level of −2.5 dBFS when using the low latency FIR
filter. This output level reduction is a result of the −1.5 dB pass-
band attenuation in the FIR filter in this mode and does not
result in loss in the dynamic range of the converter.
0
–1
–2
–3
–4 0
30.72
61.44
92.16
122.88
FILTER RESPONSE (MHz)
Figure 41. Low Latency FIR Filter Composite Response at 245.76 MSPS
(Fixed-Frequency NCO, 95 MHz FIR Filter Mode)
–1.000
–1.125
–1.250
–1.375
–1.500 0
30.72
61.44
92.16
FILTER RESPONSE (MHz)
122.88
Figure 42. Low Latency FIR Filter Pass-Band Response at 245.76 MSPS
(Fixed-Frequency NCO, 95 MHz FIR Filter Mode)
When using the tunable-frequency NCO and 100 MHz FIR filter,
the output rate is equal to the sample clock rate. The response of
the high performance FIR filter is shown in Figure 43. The detailed
pass-band response for this mode is shown in Figure 44. To place
the part into this mode, set SPI Register 0x50 to 0xA0. When
using the high performance FIR filter, the output level is −1.3 dBFS
for a corresponding input level of −1.0 dBFS at the analog inputs.
This is a result of the −0.3 dB pass-band attenuation of the FIR
filter in this mode and does not result in loss in the dynamic range
of the converter.
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0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
30.72
61.44
92.16
FILTER RESPONSE (MHz)
122.88
Figure 43. High Performance FIR Filter Pass-Band Response at 245.76 MSPS
(Tunable-Frequency NCO, 100 MHz FIR Filter)
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0
0
15.36
30.72
46.08
FILTER RESPONSE (MHz)
61.44
Figure 44. High Performance FIR Filter Pass-Band Response at 245.76 MSPS
(Tunable-Frequency NCO, 100 MHz FIR Filter)
AD6649
OUTPUT NCO
The output of the 32-bit fine-tuning NCO is complex and
typically centered in frequency around dc. This complex output
is carried through the stages of either the 95 MHz or 100 MHz FIR
filter to provide proper antialiasing filtering. The final NCO
provides a means to move this complex output signal away from
dc so that a real output can be provided from the AD6649. The
output NCO translates the output from dc to a frequency equal
to the output frequency divided by 4 (fS/4). This provides the user
with an output signal centered at fS/4 in frequency.
The AD6649 output NCOs within a single part or across
multiple parts can be synchronized using the external SYNC
input. Bit 7 and Bit 6 of Register 0x58 allow the output NCO to
be resynchronized on every SYNC signal or only on the first
SYNC signal after the register is written.
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AD6649
ADC OVERRANGE AND GAIN CONTROL
In receiver applications, it is desirable to have a mechanism to
reliably determine when the converter is about to be clipped.
The standard overflow indicator provides delayed information
on the state of the analog input that is of limited value in preventing
clipping. Therefore, it is helpful to have a programmable threshold
below full scale that allows time to reduce the gain before the clip
occurs. In addition, because input signals can have significant
slew rates, latency of this function is of concern.
Using the SPI port, the user can provide a threshold above which
the FD output is active. Bit 0 of SPI Register 0x45 allows the user to
select the threshold level. As long as the signal is below the selected
threshold, the FD output remains low. In this mode, the magnitude
of the data is considered in the calculation of the condition, but
the sign of the data is not considered. The threshold detection
responds identically to positive and negative signals outside the
desired range (magnitude).
ADC OVERRANGE (OR)
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange condition is
determined at the output of the ADC pipeline and, therefore, is
subject to a latency of 7 ADC clock cycles. An overrange at the
input is indicated by this bit 7 clock cycles after it occurs.
GAIN SWITCHING
The AD6649 includes circuitry that is useful in applications
either where large dynamic ranges exist or where gain ranging
amplifiers are employed. This circuitry allows digital thresholds
to be set such that an upper threshold and a lower threshold can
be programmed.
One such use is to detect when an ADC is about to reach full
scale with a particular input condition. The result is to provide
an indicator that can be used to quickly insert an attenuator that
prevents ADC overdrive.
Fast Threshold Detection (FDA and FDB)
The FD indicator is asserted if the input magnitude exceeds the
value programmed in the fast detect upper threshold register,
located in Register 0x47 and Register 0x48. The selected threshold
register is compared with the signal magnitude at the output of
the ADC. The fast upper threshold detection has a latency of
4 clock cycles. The upper threshold magnitude is defined by the
following equation:
Upper Threshold Magnitude (dBFS)
= 20 log(Threshold Magnitude/213)
The FD indicators are not cleared until the signal drops below
the lower threshold for the programmed dwell time. The lower
threshold is programmed in the fast detect lower threshold
register, located at Register 0x49 and Register 0x4A. The fast
detect lower threshold register is a 15-bit register that is
compared with the signal magnitude at the output of the ADC.
This comparison is subject to the ADC pipeline latency but is
accurate in terms of converter resolution. The lower threshold
magnitude is defined by the following equation:
Lower Threshold Magnitude (dBFS)
= 20 log(Threshold Magnitude/213)
The dwell time can be programmed from 1 to 65,535 sample
clock cycles by placing the desired value in the fast detect dwell
time register, located in Register 0x4B and Register 0x4C.
The operation of the upper threshold and lower threshold
registers, along with the dwell time, is shown in Figure 45.
UPPER THRESHOLD
DWELL TIME
TIMER RESET BY
RISE ABOVE LT
LOWER THRESHOLD
FDA OR FDB
DWELL TIME
Figure 45. Threshold Settings for FDA and FDB Signals
TIMER COMPLETES BEFORE
SIGNAL RISES ABOVE LT
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DC CORRECTION
Because the dc offset of the ADC may be significantly larger
than the signal being measured, a dc correction circuit is included
to null the dc offset before measuring the power. The dc correction
circuit can also be switched into the main signal path, but this
may not be appropriate if the ADC is digitizing a time-varying
signal with significant dc content, such as GSM.
DC Correction Bandwidth
The dc correction circuit is a high-pass filter with a program-
mable bandwidth (ranging between 0.29 Hz and 2.387 kHz at
245.76 MSPS). The bandwidth is controlled by writing the 4-bit
dc correction bandwidth select register, located at Register 0x40,
Bits[5:2]. The following equation can be used to compute the
bandwidth value for the dc correction circuit:
DC _ Corr _ BW = 2k 14 × fCLK
2×π
where:
k is the 4-bit value programmed in Bits[5:2] of Register 0x40
(values between 0 and 13 are valid for k; programming 14 or 15
provides the same result as programming 13).
fCLK is the AD6649 ADC sample rate in hertz.
AD6649
DC Correction Readback
The current dc correction value can be read back in Register 0x41
and Register 0x42 for each channel. The dc correction value is a
16-bit value that can span the entire input range of the ADC.
DC Correction Freeze
Setting Bit 6 of Register 0x40 freezes the DC correction at its
current state and continues to use the last updated value as the
dc correction value. Clearing this bit restarts dc correction and
adds the currently calculated value to the data.
DC Correction Enable Bits
Setting Bit 1 of Register 0x40 enables dc correction for use in
the output data signal path.
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AD6649
CHANNEL/CHIP SYNCHRONIZATION
The AD6649 has a SYNC input that allows the user flexible syn-
chronization options for synchronizing the internal blocks. The
SYNC feature is useful for guaranteeing synchronized operation
across multiple ADCs. The input clock divider, NCO, FIR filters,
and the output fS/4 NCO can be synchronized using the SYNC
input. Each of these blocks can be enabled to synchronize on a
single occurrence of the SYNC signal or on every occurrence by
setting the appropriate bits in Register 0x58.
The SYNC input is internally synchronized to the sample clock.
However, to ensure that there is no timing uncertainty between
multiple parts, the SYNC input signal should be synchronized
to the input clock signal. The SYNC input should be driven
using a single-ended CMOS type signal.
If Bit 1 in Register 0x59 is used, the SYNC input can be set to
either level or edge sensitive mode. If the SYNC input is set to
edge sensitive mode, Bit 0 of Register 0x59 can be used to
determine whether the rising or falling edge is used.
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SERIAL PORT INTERFACE (SPI)
The AD6649 serial port interface (SPI) allows the user to configure
the converter for specific functions or operations through a
structured register space provided inside the ADC. The SPI
gives the user added flexibility and customization, depending on
the application. Addresses are accessed via the serial port and
can be written to or read from via the port. Memory is organized
into bytes that can be further divided into fields. These fields are
documented in the Memory Map section. For detailed operational
information, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
CONFIGURATION USING THE SPI
Three pins define the SPI of this ADC: the SCLK pin, the
SDIO pin, and the CSB pin (see Table 13). The SCLK (serial
clock) pin is used to synchronize the read and write data presented
from/to the ADC. The SDIO (serial data input/output) pin is a
dual-purpose pin that allows data to be sent and read from the
internal ADC memory map registers. The CSB (chip select bar)
pin is an active low control that enables or disables the read and
write cycles.
Table 13. Serial Port Interface Pins
Pin Function
SCLK Serial Clock. The serial shift clock input, which is used to
synchronize serial interface reads and writes.
SDIO
Serial Data Input/Output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the
timing frame.
CSB Chip Select Bar. An active low control that gates the read
and write cycles.
The falling edge of the CSB, in conjunction with the rising edge
of the SCLK, determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure 46
and Table 5.
Other modes involving the CSB are available. The CSB can be
held low indefinitely, which permanently enables the device;
this is called streaming. The CSB can stall high between bytes
to allow for additional external timing. When CSB is tied high,
SPI functions are placed in a high impedance mode. This mode
turns on any SPI pin secondary functions.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and W1 bits.
AD6649
All data is composed of 8-bit words. The first bit of each individual
byte of serial data indicates whether a read or write command is
issued. This allows the serial data input/output (SDIO) pin to
change direction from an input to an output.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the serial data input/
output (SDIO) pin to change direction from an input to an output
at the appropriate point in the serial frame.
Data can be sent in MSB first mode or in LSB first mode. MSB
first is the default on power-up and can be changed via the SPI
port configuration register. For more information about this
and other features, see the AN-877 Application Note, Interfacing
to High Speed ADCs via SPI.
HARDWARE INTERFACE
The pins described in Table 13 comprise the physical interface
between the user programming device and the serial port of the
AD6649. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note, Micro-
controller-Based Serial Port Interface (SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used for
other devices, it may be necessary to provide buffers between
this bus and the AD6649 to prevent these signals from transi-
tioning at the converter inputs during critical sampling periods.
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AD6649
SPI ACCESSIBLE FEATURES
Table 14 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the AN-877 Application Note, Interfacing to High Speed ADCs
via SPI. The AD6649 part-specific features are described in the
Memory Map Register Description section.
Table 14. Features Accessible Using the SPI
Feature Name
Description
Mode
Allows the user to set either power-down mode or standby mode
Clock
Allows the user to access the DCS via the SPI
Offset
Allows the user to digitally adjust the converter offset
Test I/O
Allows the user to set test modes to have known data on output bits
Output Mode
Allows the user to set up outputs
Output Phase
Allows the user to set the output clock polarity
Output Delay
Allows the user to vary the DCO delay
VREF
Allows the user to set the reference voltage
Digital Processing
Allows the user to enable the NCOs, FIR filters, and synchronization features
CSB
tDS
tS
tDH
tHIGH
tLOW
tCLK
SCLK DON’T CARE
SDIO DON’T CARE
R/W W1
W0 A12 A11 A10 A9
A8
A7
tH
DON’T CARE
D5 D4 D3 D2 D1 D0 DON’T CARE
Figure 46. Serial Port Interface Timing Diagram
Rev. 0 | Page 30 of 40



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