http://www.Datasheet4U.com


AD6649 Datasheet
IF Diversity Receiver

No Preview Available !

AD6649 pdf
Download PDF File

www.DataSheet4U.net
IF Diversity Receiver
AD6649
FEATURES
APPLICATIONS
SNR = 73.0 dBFS in a 95 MHz bandwidth at
185 MHz AIN and 245.76 MSPS
SFDR = 85 dBc at 185 MHz AIN and 250 MSPS
Noise density = −151.2 dBFS/Hz input at 185 MHz, −1 dBFS
AIN and 250 MSPS
Total power consumption: 1 W with fixed-frequency NCO,
95 MHz FIR filter
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Integrated dual-channel ADC
Sample rates of up to 250 MSPS
IF sampling frequencies to 400 MHz
Internal ADC voltage reference
Flexible input range
1.4 V p-p to 2.1 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Integrated wideband digital processor
32-bit complex numerically controlled oscillator (NCO)
FIR filter with 2 modes
Real output from an fS/4 output NCO
Amplitude detect bits for efficient AGC implementation
Energy saving power-down modes
Decimated, interleaved real LVDS data outputs
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMax, WCDMA,
CDMA2000, GSM, EDGE, LTE
General-purpose software radios
Broadband data applications
GENERAL DESCRIPTION
The AD6649 is a mixed-signal intermediate frequency (IF) receiver
consisting of dual 14-bit, 250 MSPS ADCs and a wideband digital
downconverter (DDC). The AD6649 is designed to support
communications applications, where low cost, small size, wide
bandwidth, and versatility are desired.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations. A duty cycle stabilizer is provided to
compensate for variations in the ADC clock duty cycle, allowing
the converters to maintain excellent performance.
FUNCTIONAL BLOCK DIAGRAM
AVDD
FDA
DRVDD
VIN+A
VIN–A
THRESHOLD DETECT
ADC
DC
CORRECTION
I SELECTABLE
FIR
FILTER
Q SELECTABLE
FIR
FILTER
AD6649
DIGITAL
INTERLEAVING
OR+
OR–
D13+/D13–
D0+/D0–
REFERENCE
32-BIT
TUNING NCO
VIN–B
VIN+B
DC
CORRECTION
ADC
THRESHOLD DETECT
Q SELECTABLE
FIR
FILTER
I SELECTABLE
FIR
FILTER
fS/4
NCO
DIVIDE 1
TO 8
DUTY
CYCLE
STABILIZER
DCO
GENERATION
MULTICHIP
SYNC
PROGRAMMING DATA
SPI
CLK+
CLK–
DCO+
DCO–
SYNC
AGND
FDB
PDWN
OEB
SDIO SCLK CSB
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.


AD6649 Datasheet
IF Diversity Receiver

No Preview Available !

AD6649 pdf
Download PDF File

AD6649
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
General Description ......................................................................... 1 
Functional Block Diagram .............................................................. 1 
Revision History ............................................................................... 2 
Product Highlights ........................................................................... 3 
Specifications..................................................................................... 4 
ADC DC Specifications................................................................. 4 
ADC AC Specifications ................................................................. 5 
Digital Specifications ..................................................................... 6 
Switching Specifications ................................................................ 8 
Timing Specifications .................................................................. 9 
Absolute Maximum Ratings.......................................................... 10 
Thermal Characteristics ............................................................ 10 
ESD Caution................................................................................ 10 
Pin Configuration and Function Descriptions........................... 11 
Typical Performance Characteristics ........................................... 13 
Equivalent Circuits ......................................................................... 16 
Theory of Operation ...................................................................... 17 
ADC Architecture ...................................................................... 17 
Analog Input Considerations.................................................... 17 
Voltage Reference ....................................................................... 19 
Clock Input Considerations ...................................................... 19 
Power Dissipation and Standby Mode..................................... 20 
Digital Outputs ........................................................................... 21 
Digital Processing ........................................................................... 22 
Numerically Controlled Oscillator (NCO) ............................. 22 
NCO and FIR Filter Modes....................................................... 22 
REVISION HISTORY
4/11—Revision 0: Initial Version
fS/4 Fixed-Frequency NCO ....................................................... 22 
Numerically Controlled Oscillator (NCO) ................................. 23 
Frequency Translation ............................................................... 23 
NCO Synchronization ............................................................... 23 
NCO Amplitude and Phase Dither.......................................... 23 
FIR Filters ........................................................................................ 24 
FIR Synchronization .................................................................. 24 
Filter Performance...................................................................... 24 
Output NCO ............................................................................... 25 
ADC Overrange and Gain Control.............................................. 26 
ADC Overrange (OR)................................................................ 26 
Gain Switching............................................................................ 26 
DC Correction ................................................................................ 27 
Channel/Chip Synchronization.................................................... 28 
Serial Port Interface (SPI).............................................................. 29 
Configuration Using the SPI..................................................... 29 
Hardware Interface..................................................................... 29 
SPI Accessible Features.............................................................. 30 
Memory Map .................................................................................. 31 
Reading the Memory Map Register Table............................... 31 
Memory Map Register Table..................................................... 32 
Memory Map Register Description ......................................... 36 
Applications Information .............................................................. 39 
Design Guidelines ...................................................................... 39 
Outline Dimensions ....................................................................... 40 
Ordering Guide .......................................................................... 40 
Rev. 0 | Page 2 of 40


AD6649 Datasheet
IF Diversity Receiver

No Preview Available !

AD6649 pdf
Download PDF File

ADC data outputs are internally connected directly to the digital
downconverter (DDC) of the receiver. The digital receiver has
two channels and provides processing flexibility. Each receive
channel has four cascaded signal processing stages: a 32-bit
frequency translator (numerically controlled oscillator (NCO)),
an optional sample rate converter, a fixed FIR filter, and an fS/4
fixed-frequency NCO.
In addition to the receiver DDC, the AD6649 has several
functions that simplify the automatic gain control (AGC)
function in the system receiver. The programmable threshold
detector allows monitoring of the incoming signal power using
the fast detect output bits of the ADC. If the input signal level
exceeds the programmable threshold, the fast detect indicator goes
high. Because this threshold indicator has low latency, the user
can quickly turn down the system gain to avoid an overrange
condition at the ADC input.
After digital processing, data is routed directly to the 14-bit
output port. These outputs operate at ANSI or reduced swing
LVDS signal levels.
The AD6649 receiver digitizes a wide spectrum of IF frequencies.
Each receiver is designed for simultaneous reception of the main
channel and the diversity channel. This IF sampling architecture
AD6649
greatly reduces component cost and complexity compared with
traditional analog techniques or less integrated digital methods.
In diversity applications, the output data format is real due to
the final NCO, which shifts the output center frequency to fS/4.
Flexible power-down options allow significant power savings,
when desired.
Programming for setup and control is accomplished using a 3-pin
SPI-compatible serial interface.
The AD6649 is available in a 64-lead LFCSP and is specified over
the industrial temperature range of −40°C to +85°C. This
product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Integrated dual, 14-bit, 250 MSPS ADCs.
2. Integrated wideband filter and 32-bit complex NCO.
3. Fast overrange and threshold detect.
4. Proprietary differential input maintains excellent SNR
performance for input frequencies of up to 400 MHz.
5. SYNC input allows synchronization of multiple devices.
6. 3-pin, 1.8 V SPI port for register programming and register
readback.
Rev. 0 | Page 3 of 40


AD6649 Datasheet
IF Diversity Receiver

No Preview Available !

AD6649 pdf
Download PDF File

AD6649
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input,1 1.75 V p-p full-scale input range,
duty cycle stabilizer (DCS) enabled, NCO enabled, FIR filter enabled, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
MATCHING CHARACTERISTIC
Offset Error
Gain Error
TEMPERATURE DRIFT
Offset Error
Gain Error
INPUT REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span
Input Capacitance2
Input Resistance3
Input Common-Mode Voltage
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD4
IDRVDD4 (Fixed-Frequency NCO, 95 MHz FIR Filter)
IDRVDD4 (Tunable-Frequency NCO, 100 MHz FIR Filter)
POWER CONSUMPTION
Sine Wave Input (Fixed-Frequency NCO, 95 MHz FIR Filter)
Sine Wave Input (Tunable-Frequency NCO, 100 MHz FIR Filter)
Standby Power5
Power-Down Power
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min Typ
14
Max
Guaranteed
±10
−5.5 +2.5
±13
±2.5
±15
±50
1.32
1.75
2.5
20
0.9
Unit
Bits
mV
%FSR
mV
%FSR
ppm/°C
ppm/°C
LSB rms
V p-p
pF
V
1.7 1.8 1.9
1.7 1.8 1.9
V
V
271 275
283 300
375
mA
mA
mA
997
1163
104
10
1035
mW
mW
mW
mW
1 A −1.0 dBFS input level at the analog inputs corresponds to an output level of −2.5 dBFS when using the fixed-frequency NCO and 95 MHz FIR filter. When using the
tunable-frequency NCO and 100 MHz FIR filter, the output level is −1.3 dBFS. These respective output level reductions are due to FIR filter losses. See the FIR Filters
section for more details.
2 Input capacitance refers to the effective capacitance between one differential input pin and AGND.
3 Input resistance refers to the effective resistance between one differential input pin and its complement.
4 Measured with a 185 MHz, full-scale sine wave input on both channels and an NCO frequency of 62.5 MHz (fS/4).
5 Standby power is measured with a dc input and the CLK pin inactive (set to AVDD or AGND).
Rev. 0 | Page 4 of 40


AD6649 Datasheet
IF Diversity Receiver

No Preview Available !

AD6649 pdf
Download PDF File

AD6649
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input,1 1.75 V p-p full-scale input range,
DCS enabled, NCO enabled, FIR filter enabled, unless otherwise noted.
Table 2.
Parameter2
SIGNAL-TO-NOISE RATIO (SNR)3
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
WORST OTHER HARMONIC OR SPUR
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
TWO-TONE SFDR
fIN = 184.12 MHz, 187.12 MHz (−7 dBFS)
CROSSTALK4
ANALOG INPUT BANDWIDTH
Temperature
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
Full
25°C
Min Typ
74.5
74.2
73.9
73.4
70.9
72.9
73.4
73.0
72.3
71.7
68.7
71.0
−92
−88
−85
−85
−89
92
88
85
85
80
84
−95
−94
−93
−93
−84
88
95
1000
Max Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
dBc
dBc
dBc
−80 dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
−80 dBc
dBc
dBc
dB
MHz
1 A −1.0 dBFS input level at the analog inputs corresponds to an output level of −2.5 dBFS when using the fixed-frequency NCO and 95 MHz FIR filter. When using the
tunable-frequency NCO and 100 MHz FIR filter, the output level is −1.3 dBFS. These respective output level reductions are due to FIR filter losses. See the FIR Filters
section for more details.
2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
3 SNR specifications are for filtered 95 MHz bandwidth.
4 Crosstalk is measured at 100 MHz with −1 dBFS on one channel and with no input on the alternate channel.
Rev. 0 | Page 5 of 40


AD6649 datasheets pdf
Total : 30 Pages
Download Full PDF File