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AD6643 Datasheet
Dual IF Receiver 1.8V supply voltages Internal ADC voltage reference

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FEATURES
Performance with NSR enabled
SNR: 76.1 dBFS in a 40 MHz band to 90 MHz at 185 MSPS
SNR: 73.6 dBFS in a 60 MHz band to 90 MHz at 185 MSPS
Performance with NSR disabled
SNR: 66.5 dBFS up to 90 MHz at 185 MSPS
SFDR: 88 dBc up to 185 MHz at 185 MSPS
Total power consumption: 706 mW at 200 MSPS
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Internal ADC voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
Differential analog inputs with 400 MHz bandwidth
95 dB channel isolation/crosstalk
Serial port control
Energy saving power-down modes
User-configurable, built-in self test (BIST) capability
APPLICATIONS
Communications
Diversity radio and smart antenna (MIMO) systems
Multimode digital receivers (3G)
WCDMA, LTE, CDMA2000
WiMAX, TD-SCDMA
I/Q demodulation systems
General-purpose software radios
GENERAL DESCRIPTION
The AD6643 is an 11-bit, 200 MSPS, dual-channel intermediate
frequency (IF) receiver specifically designed to support multi-
antenna systems in telecommunication applications where high
dynamic range performance, low power, and small size are desired.
The device consists of two high performance analog-to-digital
converters (ADCs) and noise shaping requantizer (NSR) digital
blocks. Each ADC consists of a multistage, differential pipelined
architecture with integrated output error correction logic, and
each ADC features a wide bandwidth switched capacitor sampling
network within the first stage of the differential pipeline. An
integrated voltage reference eases design considerations. A duty
cycle stabilizer (DCS) compensates for variations in the ADC
clock duty cycle, allowing the converters to maintain excellent
performance.
Dual IF Receiver
AD6643
VIN+A
VIN–A
VCM
VIN+B
VIN–B
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DRVDD
AD6643
PIPELINE 14 NOISE SHAPING 11
ADC
REQUANTIZER
PIPELINE 14 NOISE SHAPING 11
ADC
REQUANTIZER
REFERENCE
SERIAL PORT
CLOCK
DIVIDER
DCO±
D0±
D10±
OEB
SYNC
PDWN
SCLK SDIO CSB
CLK+ CLK–
NOTES
1. THE D0± TO D10± PINS REPRESENT BOTH THE CHANNEL A
AND CHANNEL B LVDS OUTPUT DATA.
Figure 1.
Each ADC output is connected internally to an NSR block. The
integrated NSR circuitry allows for improved SNR performance in
a smaller frequency band within the Nyquist bandwidth. The
device supports two different output modes selectable via the SPI.
With the NSR feature enabled, the outputs of the ADCs are
processed such that the AD6643 supports enhanced SNR per-
formance within a limited portion of the Nyquist bandwidth
while maintaining an 11-bit output resolution.
The NSR block can be programmed to provide a bandwidth
of either 22% or 33% of the sample clock. For example, with a
sample clock rate of 185 MSPS, the AD6643 can achieve up to
75.5 dBFS SNR for a 40 MHz bandwidth in the 22% mode and
up to 73.7 dBFS SNR for a 60 MHz bandwidth in the 33% mode.
(continued on Page 3)
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.


AD6643 Datasheet
Dual IF Receiver 1.8V supply voltages Internal ADC voltage reference

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AD6643
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Product Highlights ........................................................................... 3
Specifications..................................................................................... 4
ADC DC Specifications................................................................. 4
ADC AC Specifications ................................................................. 5
Digital Specifications ..................................................................... 6
Switching Specifications ................................................................ 8
Timing Specifications .................................................................. 8
Absolute Maximum Ratings.......................................................... 10
Thermal Characteristics ............................................................ 10
ESD Caution................................................................................ 10
Pin Configurations and Function Descriptions ......................... 11
Typical Performance Characteristics ........................................... 15
Equivalent Circuits ......................................................................... 18
Theory of Operation ...................................................................... 19
ADC Architecture ...................................................................... 19
Analog Input Considerations.................................................... 19
REVISION HISTORY
4/11—Revision 0: Initial Version
Voltage Reference ....................................................................... 21
Clock Input Considerations...................................................... 21
Power Dissipation and Standby Mode .................................... 22
Digital Outputs ........................................................................... 23
Noise Shaping Requantizer (NSR) ............................................... 24
22% BW Mode (>40 MHz at 184.32 MSPS)........................... 24
33% BW Mode (>60 MHz at 184.32 MSPS)........................... 25
Channel/Chip Synchronization.................................................... 26
Serial Port Interface (SPI).............................................................. 27
Configuration Using the SPI..................................................... 27
Hardware Interface..................................................................... 27
SPI Accessible Features.............................................................. 28
Memory Map .................................................................................. 29
Reading the Memory Map Register Table............................... 29
Memory Map Register Table..................................................... 30
Memory Map Register Description ......................................... 32
Applications Information .............................................................. 34
Design Guidelines ...................................................................... 34
Outline Dimensions ....................................................................... 35
Ordering Guide .......................................................................... 35
Rev. 0 | Page 2 of 36


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When the NSR block is disabled, the ADC data is provided directly
to the output at a resolution of 11 bits. The AD6643 can achieve
up to 66.5 dBFS SNR for the entire Nyquist bandwidth when
operated in this mode. This allows the AD6643 to be used in
telecommunication applications such as a digital predistortion
observation path where wider bandwidths are required.
After digital signal processing, multiplexed output data is
routed into two 11-bit output ports such that the maximum
data rate is 400 Mbps (DDR). These outputs are LVDS and
support ANSI-644 levels.
The AD6643 receiver digitizes a wide spectrum of IF frequencies.
Each receiver is designed for simultaneous reception of a separate
antenna. This IF sampling architecture greatly reduces compo-
nent cost and complexity compared with traditional analog
techniques or less integrated digital methods.
Flexible power-down options allow significant power savings.
Programming for device setup and control is accomplished
using a 3-wire SPI-compatible serial interface with numerous
modes to support board level system testing.
AD6643
The AD6643 is available in a Pb-free, RoHS compliant, 64-lead,
9 mm × 9 mm lead frame chip scale package (LFCSP_VQ) and is
specified over the industrial temperature range of −40°C to +85°C.
This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Two ADCs are contained in a small, space-saving,
9 mm × 9 mm × 0.85 mm, 64-lead LFCSP package.
2. Pin selectable noise shaping requantizer (NSR) function
that allows for improved SNR within a reduced bandwidth
of up to 60 MHz at 185 MSPS.
3. LVDS digital output interface configured for low cost
FPGA families.
4. Operation from a single 1.8 V supply.
5. Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary or twos complement), NSR, power-down,
test modes, and voltage reference mode.
6. On-chip integer 1-to-8 input clock divider and multichip
sync function to support a wide range of clocking schemes
and multichannel subsystems.
Rev. 0 | Page 3 of 36


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AD6643
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, default SPI,
unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)1
Integral Nonlinearity (INL)1
MATCHING CHARACTERISTIC
Offset Error
Gain Error
TEMPERATURE DRIFT
Offset Error
Gain Error
INPUT REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span
Input Capacitance2
Input Resistance3
Input Common-Mode Voltage
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD1
IDRVDD1
POWER CONSUMPTION
Sine Wave Input1 (DRVDD = 1.8 V)
Standby Power4
Power-Down Power
Temperature Min
Full 11
Full
Full
Full
Full
Full
25°C
25°C
Full
Full
25°C
Full
Full
Full
Full
Typ Max
Guaranteed
±10
+2/−6
±0.1 ±0.25
±0.2 ±0.25
±13
−2/+3.5
±15
±50
0.614
1.75
2.5
20
0.9
Unit
Bits
mV
% FSR
LSB
LSB
mV
% FSR
ppm/°C
ppm/°C
LSB rms
V p-p
pF
V
Full
1.7 1.8
1.9
V
Full
1.7 1.8
1.9
V
Full
238 260
mA
Full
154 215
mA
Full
706 855
mW
Full 90 mW
Full 10 mW
1 Measured using a 10 MHz, 0 dBFS sine wave, and 100 Ω termination on each LVDS output pair.
2 Input capacitance refers to the effective capacitance between one differential input pin and its complement.
3 Input resistance refers to the effective resistance between one differential input pin and its complement.
4 Standby power is measured using a dc input and the CLK± pins inactive (set to AVDD or AGND).
Rev. 0 | Page 4 of 36


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AD6643
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, default SPI,
unless otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE-RATIO (SNR)
NSR Disabled
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
NSR Enabled
22% BW Mode
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
33% BW Mode
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
SIGNAL-TO-NOISE-AND-DISTORTION (SINAD)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
WORST OTHER HARMONIC OR SPUR
fIN = 30 MHz
fIN = 90 MHz
fIN = 140 MHz
fIN = 185 MHz
fIN = 220 MHz
Temperature
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
Min Typ
Max Unit
66.6
66.5
66.2
66.4
66.2
66.0
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
76.1 dBFS
75.5 dBFS
74.7 dBFS
74.2 dBFS
73.6 dBFS
73.1 dBFS
72.6 dBFS
72.1 dBFS
65.6
65.5
65.1
65.3
65.1
64.9
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
−92 dBc
−91 dBc
−80 dBc
−88 dBc
−88 dBc
−84 dBc
92
91
80
88
88
84
dBc
dBc
dBc
dBc
dBc
dBc
−94 dBc
−94 dBc
−80 dBc
−95 dBc
−94 dBc
−93 dBc
Rev. 0 | Page 5 of 36


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