Dual IF Receiver 1.8V supply voltages Internal ADC voltage reference
No Preview Available !
Download PDF File
THEORY OF OPERATION
The AD6643 has two analog input channels and two digital
output channels. The intermediate frequency (IF) input signal
passes through several stages before appearing at the output
port(s) as a filtered, and optionally decimated, digital signal.
The AD6643 architecture consists of dual front-end sample-
and-hold circuits, followed by pipelined, switched capacitor
ADCs. The quantized outputs from each stage are combined
into a final 11-bit result in the digital correction logic. Alternately,
the 11-bit result can be processed through the noise shaping
requantizer (NSR) block before it is sent to the digital correc-
The pipelined architecture permits the first stage to operate on
a new input sample and the remaining stages to operate on the
preceding samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor digital-
to-analog converter (DAC) and an interstage residue amplifier
(MDAC). The residue amplifier magnifies the difference between
the reconstructed DAC output and the flash input for the next
stage in the pipeline. One bit of redundancy is used in each stage
to facilitate digital correction of flash errors. The last stage simply
consists of a flash ADC.
The input stage of each channel contains a differential sampling
circuit that can be ac- or dc-coupled in differential or single-ended
modes. The output staging block aligns the data, corrects errors,
and passes the data to the output buffers. The output buffers are
powered from a separate supply, allowing adjustment of the out-
put drive current. During power-down, the output buffers enter
a high impedance state.
The AD6643 dual IF receiver can simultaneously digitize two
channels, making it ideal for diversity reception and digital pre-
distortion (DPD) observation paths in telecommunication systems.
The dual IF receiver design can be used for diversity reception
of signals, whereas the ADCs operate identically on the same
carrier but from two separate antennae. The ADCs can also be
operated with independent analog inputs. The user can input
frequencies from dc to 300 MHz using appropriate low-pass or
band-pass filtering at the ADC inputs with little loss in
performance. Operation to 400 MHz analog input is permitted
but occurs at the expense of increased ADC noise and distortion.
Synchronization capability is provided to allow synchronized
timing between multiple devices.
Programming and control of the AD6643 are accomplished
using a 3-wire SPI-compatible serial interface.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD6643 is a differential switched capacitor
circuit designed for optimum performance in differential signal
The clock signal alternatively switches the input between sample
mode and hold mode (see Figure 27). When the input is switched
into sample mode, the signal source must be capable of charging
the sample capacitors and settling within 1/2 of a clock cycle.
A small resistor in series with each input can help reduce the peak
transient current required from the output stage of the driving
source. A shunt capacitor can be placed across the inputs to
provide dynamic charging currents. This passive network creates
a low-pass filter at the ADC input; therefore, the precise values
are dependent on the application.
In intermediate frequency (IF) undersampling applications, any
shunt capacitors placed across the inputs should be reduced. In
combination with the driving source impedance, the shunt capa-
citors limit the input bandwidth. For more information, refer to
the AN-742 Application Note, Frequency Domain Response of
Switched-Capacitor ADCs; the AN-827 Application Note, A
Resonant Approach to Interfacing Amplifiers to Switched-Capacitor
ADCs; and the Analog Dialogue article, “Transformer-Coupled
Front-End for Wideband A/D Converters,” available at
Figure 27. Switched Capacitor Input
For best dynamic performance, match the source impedances
driving VIN+ and VIN− and differentially balance the inputs.
Input Common Mode
The analog inputs of the AD6643 are not internally dc biased.
In ac-coupled applications, the user must provide this bias exter-
nally. Setting the device so that VCM = 0.5 × AVDD (or 0.9 V)
is recommended for optimum performance.
An on-board common-mode voltage reference is included in the
design and is available from the VCM pin. Using the VCM output
to set the input common mode is recommended. Optimum perfor-
mance is achieved when the common-mode voltage of the analog
input is set by the VCM pin voltage (typically 0.5 × AVDD). The
VCM pin must be decoupled to ground by a 0.1 μF capacitor, as
described in the Applications Information section. Place this
Rev. 0 | Page 19 of 36