http://www.Datasheet4U.com


AD6641 Datasheet
250 MHz Bandwidth DPD Observation Receiver

No Preview Available !

AD6641 pdf
Download PDF File

www.DataSheet4U.net
250 MHz Bandwidth
DPD Observation Receiver
AD6641
FEATURES
GENERAL DESCRIPTION
SNR = 65.8 dBFS at fIN up to 250 MHz at 500 MSPS
ENOB of 10.5 bits at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS)
SFDR = 80 dBc at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS)
Excellent linearity
DNL = ±0.5 LSB typical, INL = ±0.6 LSB typical
Integrated 16k × 12 FIFO
FIFO readback options
12-bit parallel CMOS at 62.5 MHz
6-bit DDR LVDS interface
SPORT at 62.5 MHz
SPI at 25 MHz
High speed synchronization capability
1 GHz full power analog bandwidth
Integrated input buffer
On-chip reference, no external decoupling required
Low power dissipation
695 mW at 500 MSPS
Programmable input voltage range
1.18 V to 1.6 V, 1.5 V nominal
1.9 V analog and digital supply operation
1.9 V or 3.3 V SPI and SPORT operation
Clock duty cycle stabilizer
Integrated data clock output with programmable clock and
data alignment
The AD6641 is a 250 MHz bandwidth digital predistortion
(DPD) observation receiver that integrates a 12-bit 500 MSPS
ADC, a 16k × 12 FIFO, and a multimode back end that allows
users to retrieve the data through a serial port (SPORT), the SPI
interface, a 12-bit parallel CMOS port, or a 6-bit DDR LVDS
port after being stored in the integrated FIFO memory. It is opti-
mized for outstanding dynamic performance and low power
consumption and is suitable for use in telecommunications
applications such as a digital predistortion observation path
where wider bandwidths are desired. All necessary functions,
including the sample-and-hold and voltage reference, are
included on the chip to provide a complete signal conversion
solution.
The on-chip FIFO allows small snapshots of time to be captured
via the ADC and read back at a lower rate. This reduces the
constraints of signal processing by transferring the captured
data at an arbitrary time and at a much lower sample rate. The
FIFO can be operated in several user-programmable modes. In
the single capture mode, the ADC data is captured when sig-
naled via the SPI port or the use of the external FILL± pins. In
the continuous capture mode, the data is loaded continuously
into the FIFO and the FILL± pins are used to stop this operation.
APPLICATIONS
Wireless and wired broadband communications
Communications test equipment
Power amplifier linearization
FUNCTIONAL BLOCK DIAGRAM
FILL+ FILL– DUMP
CLK+
CLK–
VIN+
VIN–
CLOCK AND CONTROL
ADC
FIFO
16k × 12
PARALLEL
AND
SPORT
OUTPUTS
SPI CONTROL
REFERENCE AND DATA
VREF SCLK, SDIO, AND CSB
Figure 1.
PCLK+
PCLK–
PD[5:0]± IN DDR LVDS MODE
OR PD[11:0] IN CMOS MODE
SP_SCLK
SP_SDFS
SP_SDO
FULL
EMPTY
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.


AD6641 Datasheet
250 MHz Bandwidth DPD Observation Receiver

No Preview Available !

AD6641 pdf
Download PDF File

AD6641
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
General Description ......................................................................... 1 
Functional Block Diagram .............................................................. 1 
Revision History ............................................................................... 2 
Product Highlights ........................................................................... 3 
Specifications..................................................................................... 4 
DC Specifications ......................................................................... 4 
AC Specifications.......................................................................... 5 
Digital Specifications ................................................................... 6 
Switching Specifications .............................................................. 7 
SPI Timing Requirements ........................................................... 8 
Absolute Maximum Ratings.......................................................... 10 
REVISION HISTORY
4/11—Revision 0: Initial Version
Thermal Resistance .................................................................... 10 
ESD Caution................................................................................ 10 
Pin Configurations and Function Descriptions ......................... 11 
Typical Performance Characteristics ........................................... 15 
Equivalent Circuits......................................................................... 18 
SPI Register Map ............................................................................ 20 
Theory of Operation ...................................................................... 23 
FIFO Operation.......................................................................... 23 
FIFO Output Interfaces ............................................................. 26 
Configuration Using the SPI..................................................... 27 
Outline Dimensions ....................................................................... 28 
Ordering Guide .......................................................................... 28 
Rev. 0 | Page 2 of 28


AD6641 Datasheet
250 MHz Bandwidth DPD Observation Receiver

No Preview Available !

AD6641 pdf
Download PDF File

The data stored in the FIFO can be read back based on several
user-selectable output modes. The DUMP pin can be asserted
to output the FIFO data. The data stored in the FIFO can be
accessed via a SPORT, SPI, 12-bit parallel CMOS port, or 6-bit
DDR LVDS interface. The maximum output throughput
supported by the AD6641 is in the 12-bit CMOS or 6-bit DDR
LVDS mode and is internally limited to 1/8th of the maximum
input sample rate. This corresponds to the maximum output
data rate of 62.5 MHz at an input clock rate of 500 MSPS.
The ADC requires a 1.9 V analog voltage supply and a differen-
tial clock for full performance operation. Output format options
include twos complement, offset binary format, or Gray code. A
data clock output is available for proper output data timing. Fabri-
cated on an advanced SiGe BiCMOS process, the device is
available in a 56-lead LFCSP and is specified over the industrial
temperature range (−40°C to +85°C). This product is protected
by a U.S. patent.
AD6641
PRODUCT HIGHLIGHTS
1. High Performance ADC Core.
Maintains 65.8 dBFS SNR at 500 MSPS with a 250 MHz input.
2. Low Power.
Consumes only 695 mW at 500 MSPS.
3. Ease of Use.
On-chip 16k FIFO allows the user to target the high perfor-
mance ADC to the time period of interest and reduce the
constraints of processing the data by transferring it at an
arbitrary time and a lower sample rate. The on-chip refer-
ence and sample-and-hold provide flexibility in system
design. Use of a single 1.9 V supply simplifies system power
supply design.
4. Serial Port Control.
Standard serial port interface supports configuration of the
device and customization for the user’s needs.
5. 1.9 V or 3.3 V SPI and Serial Data Port Operation.
Rev. 0 | Page 3 of 28


AD6641 Datasheet
250 MHz Bandwidth DPD Observation Receiver

No Preview Available !

AD6641 pdf
Download PDF File

AD6641
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.9 V, DRVDD = 1.9 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Table 1.
Parameter1
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
ANALOG INPUTS (VIN±)
Differential Input Voltage Range2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance (Differential)
POWER SUPPLY
AVDD
DRVDD
SPI_VDDIO
Supply Currents
IAVDD3
IDRVDD3
Power Dissipation3
Power-Down Dissipation
Standby Dissipation
Standby to Power-Up Time
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
AD6641-500
Min Typ
Max
12
Guaranteed
−2.6 0.0
+1.8
−6.8 −2.3 +3.3
±0.5
±0.6
18
0.07
1.18 1.5
1.8
1
1.3
1.6
1.8 1.9
1.8 1.9
1.8 1.9
2.0
2.0
3.3
300 330
66 80
695 779
15
72
10
Unit
Bits
mV
% FS
LSB
LSB
μV/°C
%/°C
V p-p
V
pF
V
V
V
mA
mA
mW
mW
mW
μs
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were
completed.
2 The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the SPI Register Map section for additional
details.
3 IAVDD and IDRVDD are measured with a −1 dBFS, 30 MHz sine input at a rated sample rate.
Rev. 0 | Page 4 of 28


AD6641 Datasheet
250 MHz Bandwidth DPD Observation Receiver

No Preview Available !

AD6641 pdf
Download PDF File

AD6641
AC SPECIFICATIONS
AVDD = 1.9 V, DRVDD = 1.9 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Table 2.
Parameter1, 2
SNR
fIN = 30 MHz
fIN = 125 MHz
fIN = 250 MHz
fIN = 450 MHz
SINAD
fIN = 30 MHz
fIN = 125 MHz
fIN = 250 MHz
fIN = 450 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 30 MHz
fIN = 125 MHz
fIN = 250 MHz
fIN = 450 MHz
SFDR
fIN = 30 MHz
fIN = 125 MHz
fIN = 250 MHz
fIN = 450 MHz
WORST HARMONIC (SECOND OR THIRD)
fIN = 30 MHz
fIN = 125 MHz
fIN = 250 MHz
fIN = 450 MHz
WORST OTHER HARMONIC (SFDR EXCLUDING SECOND AND THIRD)
fIN = 30 MHz
fIN = 125 MHz
fIN = 250 MHz
fIN = 450 MHz
TWO-TONE IMD
fIN1 = 119.8 MHz, fIN2 = 125.8 MHz (−7 dBFS, Each Tone)
ANALOG INPUT BANDWIDTH
Temp
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
AD6641-500
Min Typ Max
66.0
65.9
65.0
65.8
65.1
66.0
65.7
63.8
65.3
64.6
10.7
10.6
10.5
10.4
88
83
77
80
72
−92
−77
−84
−80
−72
−90
−90
−77
−85
−78
−82
1
Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
GHz
1 All ac specifications tested by driving CLK+ and CLK− differentially.
2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were
completed.
Rev. 0 | Page 5 of 28


AD6641 datasheets pdf
Total : 28 Pages
Download Full PDF File