The AD6642 is an 11-bit, 200 MSPS, dual-channel intermediate
frequency (IF) receiver specifically designed to support multi-
antenna systems in telecommunication applications where high
dynamic range performance, low power, and small size are desired.
The device consists of two high performance analog-to-digital
converters (ADCs) and noise shaping requantizer (NSR) digital
blocks. Each ADC consists of a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC features a wide bandwidth switched-capacitor sampling
network within the first stage of the differential pipeline. An
integrated voltage reference eases design considerations. A duty
cycle stabilizer (DCS) compensates for variations in the ADC
clock duty cycle, allowing the converters to maintain excellent
Each ADC output is connected internally to an NSR block. The
integrated NSR circuitry allows for improved SNR performance
in a smaller frequency band within the Nyquist bandwidth. The
device supports two different output modes selectable via the
external MODE pin or the SPI.
With the NSR feature enabled, the outputs of the ADCs are
processed such that the AD6642 supports enhanced SNR
performance within a limited portion of the Nyquist bandwidth
while maintaining an 11-bit output resolution. The NSR block
can be programmed to provide a bandwidth of either 22% or
33% of the sample clock. For example, with a sample clock rate
of 185 MSPS, the AD6642 can achieve up to 75.5 dBFS SNR for
a 40 MHz bandwidth in the 22% mode and up to 73.7 dBFS
SNR for a 60 MHz bandwidth in the 33% mode.
With the NSR block disabled, the ADC data is provided directly to
the output with a resolution of 11 bits. The AD6642 can achieve
up to 66.5 dBFS SNR for the entire Nyquist bandwidth when
operated in this mode. This allows the AD6642 to be used in
telecommunication applications such as a digital predistortion
observation path where wider bandwidths are desired.
After digital signal processing, multiplexed output data is
routed into two 11-bit output ports such that the maximum
data rate is 400 Mbps (DDR). These outputs are set at 1.8 V
LVDS and support ANSI-644 levels.
The AD6642 receiver digitizes a wide spectrum of IF frequencies.
Each receiver is designed for simultaneous reception of a separate
antenna. This IF sampling architecture greatly reduces compo-
nent cost and complexity compared with traditional analog
techniques or less integrated digital methods.
Flexible power-down options allow significant power savings.
Programming for device setup and control is accomplished
using a 3-wire SPI-compatible serial interface with numerous
modes to support board-level system testing.
The AD6642 is available in a Pb-free/RoHS compliant, 144-ball,
10 mm × 10 mm chip scale package ball grid array (CSP_BGA)
and is specified over the industrial temperature range of −40°C
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