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AD6642 Datasheet
Dual IF Receiver

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FEATURES
11-bit, 200 MSPS output data rate per channel
Integrated noise shaping requantizer (NSR)
Performance with NSR enabled
SNR: 75.5 dBFS in 40 MHz band to 70 MHz @ 185 MSPS
SNR: 73.7 dBFS in 60 MHz band to 70 MHz @ 185 MSPS
Performance with NSR disabled
SNR: 66.5 dBFS to 70 MHz @ 185 MSPS
SFDR: 83 dBc to 70 MHz @ 185 MSPS
Low power: 0.62 W @ 185 MSPS
1.8 V analog supply operation
1.8 V LVDS (ANSI-644 levels) output
1-to-8 integer clock divider
Internal ADC voltage reference
1.75 V p-p analog input range (programmable to 2.0 V p-p)
Differential analog inputs with 800 MHz bandwidth
95 dB channel isolation/crosstalk
Serial port control
User-configurable built-in self-test (BIST) capability
Energy-saving power-down modes
APPLICATIONS
Communications
Diversity radio and smart antenna (MIMO) systems
Multimode digital receivers (3G)
WCDMA, LTE, CDMA2000
WiMAX, TD-SCDMA
I/Q demodulation systems
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Dual IF Receiver
AD6642
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND DRVDD DRGND
VIN+A
VIN–A
VCMA
VIN+B
VIN–B
VCMB
AD6642
PIPELINE 14 NOISE SHAPING 11
ADC
REQUANTIZER
PIPELINE 14 NOISE SHAPING 11
ADC
REQUANTIZER
REFERENCE
SERIAL PORT
CLOCK
DIVIDER
DC0±AB
D0±AB
D10±AB
MODE
SYNC
PDWN
SCLK SDIO CSB
Figure 1.
CLK+ CLK–
PRODUCT HIGHLIGHTS
1. Two ADCs are contained in a small, space-saving,
10 mm × 10 mm × 1.4 mm, 144-ball CSP_BGA package.
2. Pin selectable noise shaping requantizer (NSR) function
that allows for improved SNR within a reduced bandwidth
of up to 60 MHz at 185 MSPS.
3. LVDS digital output interface configured for low cost
FPGA families.
4. 120 mW per ADC core power consumption.
5. Operation from a single 1.8 V supply.
6. Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary or twos complement), NSR, power-down,
test modes, and voltage reference mode.
7. On-chip integer 1-to-8 input clock divider and multichip
sync function to support a wide range of clocking schemes
and multichannel subsystems.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.


AD6642 Datasheet
Dual IF Receiver

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AD6642
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
Functional Block Diagram .............................................................. 1 
Product Highlights ........................................................................... 1 
Revision History ............................................................................... 2 
General Description ......................................................................... 3 
Specifications..................................................................................... 4 
DC Specifications ......................................................................... 4 
AC Specifications.......................................................................... 5 
Digital Specifications ................................................................... 6 
Switching Specifications .............................................................. 7 
Timing Specifications .................................................................. 8 
Absolute Maximum Ratings............................................................ 9 
Thermal Characteristics .............................................................. 9 
ESD Caution.................................................................................. 9 
Pin Configuration and Function Descriptions........................... 10 
Typical Performance Characteristics ........................................... 12 
Equivalent Circuits ......................................................................... 15 
Theory of Operation ...................................................................... 16 
ADC Architecture ...................................................................... 16 
Analog Input Considerations.................................................... 16 
Clock Input Considerations ...................................................... 18 
REVISION HISTORY
ww1w0/.D09ataSRheeveits4iUon.co0m: Initial Version
Power Dissipation and Standby Mode .................................... 20 
Channel/Chip Synchronization................................................ 20 
Digital Outputs ........................................................................... 21 
Timing ......................................................................................... 21 
Noise Shaping Requantizer (NSR) ............................................... 22 
22% BW Mode (>40 MHz @ 184.32 MSPS)........................... 22 
33% BW Mode (>60 MHz @ 184.32 MSPS)........................... 22 
MODE Pin................................................................................... 23 
Built-In Self-Test (BIST) and Output Test .................................. 24 
Built-In Self-Test (BIST)............................................................ 24 
Output Test Modes..................................................................... 24 
Serial Port Interface (SPI).............................................................. 25 
Configuration Using the SPI..................................................... 25 
Hardware Interface..................................................................... 25 
Memory Map .................................................................................. 26 
Reading the Memory Map Register Table............................... 26 
Memory Map Register Table..................................................... 27 
Memory Map Register Descriptions........................................ 29 
Applications Information .............................................................. 30 
Design Guidelines ...................................................................... 30 
Outline Dimensions ....................................................................... 31 
Ordering Guide .......................................................................... 31 
Rev. 0 | Page 2 of 32


AD6642 Datasheet
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GENERAL DESCRIPTION
The AD6642 is an 11-bit, 200 MSPS, dual-channel intermediate
frequency (IF) receiver specifically designed to support multi-
antenna systems in telecommunication applications where high
dynamic range performance, low power, and small size are desired.
The device consists of two high performance analog-to-digital
converters (ADCs) and noise shaping requantizer (NSR) digital
blocks. Each ADC consists of a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC features a wide bandwidth switched-capacitor sampling
network within the first stage of the differential pipeline. An
integrated voltage reference eases design considerations. A duty
cycle stabilizer (DCS) compensates for variations in the ADC
clock duty cycle, allowing the converters to maintain excellent
performance.
Each ADC output is connected internally to an NSR block. The
integrated NSR circuitry allows for improved SNR performance
in a smaller frequency band within the Nyquist bandwidth. The
device supports two different output modes selectable via the
external MODE pin or the SPI.
With the NSR feature enabled, the outputs of the ADCs are
processed such that the AD6642 supports enhanced SNR
performance within a limited portion of the Nyquist bandwidth
while maintaining an 11-bit output resolution. The NSR block
can be programmed to provide a bandwidth of either 22% or
33% of the sample clock. For example, with a sample clock rate
of 185 MSPS, the AD6642 can achieve up to 75.5 dBFS SNR for
a 40 MHz bandwidth in the 22% mode and up to 73.7 dBFS
SNR for a 60 MHz bandwidth in the 33% mode.
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AD6642
With the NSR block disabled, the ADC data is provided directly to
the output with a resolution of 11 bits. The AD6642 can achieve
up to 66.5 dBFS SNR for the entire Nyquist bandwidth when
operated in this mode. This allows the AD6642 to be used in
telecommunication applications such as a digital predistortion
observation path where wider bandwidths are desired.
After digital signal processing, multiplexed output data is
routed into two 11-bit output ports such that the maximum
data rate is 400 Mbps (DDR). These outputs are set at 1.8 V
LVDS and support ANSI-644 levels.
The AD6642 receiver digitizes a wide spectrum of IF frequencies.
Each receiver is designed for simultaneous reception of a separate
antenna. This IF sampling architecture greatly reduces compo-
nent cost and complexity compared with traditional analog
techniques or less integrated digital methods.
Flexible power-down options allow significant power savings.
Programming for device setup and control is accomplished
using a 3-wire SPI-compatible serial interface with numerous
modes to support board-level system testing.
The AD6642 is available in a Pb-free/RoHS compliant, 144-ball,
10 mm × 10 mm chip scale package ball grid array (CSP_BGA)
and is specified over the industrial temperature range of −40°C
to +85°C.
Rev. 0 | Page 3 of 32


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Dual IF Receiver

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AD6642
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)1
Integral Nonlinearity (INL)1
MATCHING CHARACTERISTIC
Offset Error
Gain Error
TEMPERATURE DRIFT
Offset Error
Gain Error
ANALOG INPUT
Input Range
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance2
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD1
IDRVDD1 (1.8 V LVDS)
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POWER CONSUMPTION
Sine Wave Input1
Standby Power3
Power-Down Power
Temperature Min
Full 11
Full
Full −4.5
Full
Full
Full
Full −2.4
Full
Full
Full
Full 1.4
Full
Full
Full
Full 1.7
Full 1.7
Full
Full
Full
Full
Full
Typ Max
Guaranteed
2
±3
±0.1
±0.2
7.4
±7
±0.5
±0.5
2.5 8.3
±1 ±3
2
40
1.75 2.0
0.9
20
5
1.8 1.9
1.8 1.9
265 291
79 89
619 684
83
4.5 18
Unit
Bits
mV
% FSR
LSB
LSB
mV
% FSR
ppm/°C
ppm/°C
V p-p
V
pF
V
V
mA
mA
mW
mW
mW
1 Measured with a 10 MHz, 0 dBFS sine wave, with 100 Ω termination on each LVDS output pair.
2 Input capacitance refers to the effective capacitance between one differential input pin and AGND.
3 Standby power is measured with a dc input and the CLKx pins inactive (set to AVDD or AGND).
Rev. 0 | Page 4 of 32


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AD6642
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE-RATIO (SNR)—NSR DISABLED
fIN = 30 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 250 MHz
SIGNAL-TO-NOISE-RATIO (SNR)—NSR ENABLED
22% BW Mode
fIN = 70 MHz
fIN = 170 MHz
fIN = 230 MHz
33% BW Mode
fIN = 70 MHz
fIN = 170 MHz
fIN = 230 MHz
SIGNAL-TO-NOISE-AND DISTORTION (SINAD)
fIN = 30 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 250 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 30 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 250 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 30 MHz
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fIN = 170 MHz
fIN = 250 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 30 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 250 MHz
WORST OTHER HARMONIC (FOURTH THROUGH EIGHTH)
fIN = 30 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 250 MHz
TWO-TONE SFDR (−7 dBFS)
fIN1 = 169 MHz, fIN2 = 172 MHz
CROSSTALK2
ANALOG INPUT BANDWIDTH
Temperature Min
25°C
25°C
Full 65.7
25°C
25°C
Full 72.8
25°C
25°C
Full 71.0
25°C
25°C
25°C
Full 64.1
25°C
25°C
25°C
Full 10.3
25°C
25°C
25°C
Full −72
25°C
25°C
25°C
Full 72
25°C
25°C
25°C
Full −82
25°C
25°C
Full
25°C
Typ
66.5
66.5
66.1
65.5
75.5
74.4
72.8
73.7
72.6
71.0
65.5
66.3
65.6
64.3
10.6
10.7
10.6
10.3
−90
−83
−78
−80
90
83
78
80
−100
−96
−90
−95
82
95
800
Max
Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dB
MHz
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2 Crosstalk is measured at 155 MHz with −1 dBFS on one channel and no input on the alternate channel.
Rev. 0 | Page 5 of 32


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