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IC62LV12816DL Datasheet
128 K x 16 bit Low Voltage and Ultra Low Power CMOS Static RAM

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IC62LV12816DL
IC62LV12816DLL
Document Title
128 K x 16 bit Low Voltage and Ultra Low Power CMOS Static RAM
Revision History
Revision No
0A
History
Initial Draft
Draft Date
June 7,2002
Remark
Preliminary
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
LPSR025-0A 6/7/2002
1


IC62LV12816DL Datasheet
128 K x 16 bit Low Voltage and Ultra Low Power CMOS Static RAM

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IC62LV12816DL pdf
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IC62LV12816DL
IC62LV12816DLL
128K x 16 LOW VOLTAGE, ULTRA
LOW POWER CMOS STATIC RAM
Preliminary
FEATURES
• High-speed access times: 55, 70, 100 ns
CMOS low power operation
--60mW (typical)* operating
--3µW (typical)* CMOS standby
• TTL compatible interface levels
• Single 2.7V-3.6V Vcc power supply
• Fully static operation: no clock or refresh re-
quired
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Available in the 44-pin TSOP-2 and 48-pin
6x8mm TF-BGA
• CE2 pin only for 48-pin TF-BGA.
* Typical values are measured at VCC=3.0V, TA=25°C
DESCRIPTION
The ICSI IC62LV12816DL and IC62LV12816DLL are low-
power,2,097,152 bit static RAMs organized as 131,072 words
by 16 bits. They are fabricated using ICSI's high-performance
CMOS technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-performance
and low power consumption devices.
When CE1 is HIGH or when CE2 is low (deselected) or both LB
and UB are HIGH, the device assumes a standby mode at
which the power dissipation can be reduced by using CMOS
input levels.
Easy memory expansion is provided by using Chip Enable
Output and Enable inputs, CE1, CE2 and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower Byte
(LB) access.
The IC62LV12816DL and IC62LV12816DLL are packaged in
the JEDEC standare 44-pin TSOP-2 and 48-pin 6*8mm TF-
BGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128K x 16
MEMORY ARRAY
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
CE1, CE2
OE
WE
UB
LB
CONTROL
CIRCUIT
COLUMN I/O
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2 Integrated Circuit Solution Inc.
LPSR025-0A 6/7/2002


IC62LV12816DL Datasheet
128 K x 16 bit Low Voltage and Ultra Low Power CMOS Static RAM

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IC62LV12816DL
IC62LV12816DLL
PIN CONFIGURATIONS
44-Pin TSOP-2
A4
A3
A2
A1
A0
CE1
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 A5
43 A6
42 A7
41 OE
40 UB
39 LB
38 I/O15
37 I/O14
36 I/O13
35 I/O12
34 GND
33 Vcc
32 I/O11
31 I/O10
30 I/O9
29 I/O8
28 NC
27 A8
26 A9
25 A10
24 A11
23 NC
48-Pin TF-BGA (TOP View)
1 2 34 5 6
A LB OE A0 A1 A2 CE2
B I/O8 UB A3 A4 CE1 I/O0
C I/O9 I/O10 A5 A6 I/O1 I/O2
D GND I/O11 NC A7 I/O3 Vcc
E Vcc I/O12 NC A16 I/O4 GND
F I/O14 I/O13 A14 A15 I/O5 I/O6
G I/O15 NC A12 A13 WE I/O7
H NC A8 A9 A10 A11 NC
PIN DESCRIPTIONS
A0-A16
I/O0-I/O15
Address Inputs
Data Input/Output
CE1 Chip Enable1 Input
CE2 Chip Enable2 Input, BGA only
OE Output Enable Input
WE Write Enable Input
LB
UB
NC
Vcc
GND
Lower-byte Control (l/O0-I/O7)
Upper-byte Control (l/O8-I/O15)
No Connection
Power
Ground
TRUTH TABLE
Mode
WE
Not Selected
Output Disabled
Read
Write
X
X
X
H
H
H
H
H
L
L
L
CE1
H
X
L
L
L
L
L
L
L
L
L
CE2
X
L
H
H
H
H
H
H
H
H
H
OE
X
X
X
H
H
L
L
L
X
X
X
LB
X
X
H
L
X
L
H
L
L
H
L
UB
X
X
H
X
L
H
L
L
H
L
L
I/O0/-I/O7
High-Z
High-Z
High-Z
High-Z
High-Z
DOUT
High-Z
DOUT
DIN
High-Z
DIN
I/O PIN
I/O8-I/O15
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DOUT
DOUT
High-Z
DIN
DIN
Vcc Current
Standby
Standby
Standby
Active
Active
Active
Active
Active
Active
Active
Active
Integrated Circuit Solution Inc.
LPSR025-0A 6/7/2002
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IC62LV12816DL Datasheet
128 K x 16 bit Low Voltage and Ultra Low Power CMOS Static RAM

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IC62LV12816DL
IC62LV12816DLL
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VCC
2.7V- 3.6V
2.7V - 3.6V
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
VTERM Terminal Voltage with Respect to GND –0.5 to Vcc + 0.5 V
TBIAS
Temperature Under Bias
–40 to +85
°C
VCC Vcc related to GND
–0.3 to +4.0
V
TSTG
Storage Temperature
–65 to +150
°C
PT Power Dissipation
1.0 W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
VOH
Output HIGH Voltage
IOH = –1 mA
VOL Output LOW Voltage IOL = 2.1 mA
VIH(1)
Input HIGH Voltage
VIL(2)
Input LOW Voltage(1)
ILI Input Leakage
GND VIN VCC
ILO Output Leakage
GND VOUT VCC, OUTPUTS DISABLED
Notes:
1. VIH(max.) = Vcc + 0.2V for pulse width less than 10ns.
2. VIL(min.) = –2.0V for pulse width less than 10 ns.
Min. Max. Unit
2.0 —
V
— 0.4 V
2.2
–0.2
–1
–1
VCC + 0.2
0.4
1
1
V
V
µA
µA
CAPACITANCE(1)
Symbol
Parameter
Conditions
Max.
Unit
CIN Input Capacitance
VIN = 0V
6 pF
COUT
Output Capacitance
VOUT = 0V
8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
4 Integrated Circuit Solution Inc.
LPSR025-0A 6/7/2002


IC62LV12816DL Datasheet
128 K x 16 bit Low Voltage and Ultra Low Power CMOS Static RAM

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IC62LV12816DL pdf
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IC62LV12816DL
IC62LV12816DLL
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0.4V to 2.2V
5 ns
1.3V
See Figures 1 and 2
AC TEST LOADS
OUTPUT
1 TTL
100 pF
Including
jig and
scope
Figure 1
OUTPUT
1 TTL
5 pF
Including
jig and
scope
Figure 2
IC62LV12816DL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
Test Conditions
-55 -70 -100
Min. Max. Min. Max. Min. Max.
ICC Vcc Dynamic Operating VCC = 3.0V.,
Com. — 40
Supply Current
IOUT = 0 mA, f = fMAX
Ind. — 45
— 30
— 35
— 20
— 25
ISB1 TTL Standby Current VCC = Max.,
Com. — 0.5
(TTL Inputs)
VIN = VIH or VIL, f = 0
Ind. — 1.0
CE1 = VIH, CE2 = VIL
— 0.5
— 1.0
— 0.5
— 1.0
ISB2 CMOS Standby
VCC = Max.,
Com. — 35
Current (CMOS Inputs) CE1 VCC – 0.2V,
Ind. — 50
or CE2 0.2V
other input = 0-VCC, f = 0
OR
— 35
— 50
— 35
— 50
Unit
mA
mA
µA
ULB Control
VCC = Max., CE1 = VIL, CE2 = VIH
VIN 0.2V, f = 0, UB / LB = VCC – 0.2V
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Circuit Solution Inc.
LPSR025-0A 6/7/2002
5


IC62LV12816DL datasheets pdf
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