IA64F3048SEC Datasheet

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Advance Information Sheet
8 Kbytes SRAM
129 Kbytes Flash Memory A (includes 1Kbyte security bits & trim flash)
32 Kbytes Flash Memory B
Additional 32 x 32 multiply instruction
50MHz Clock Rate
FWE pin changed to BME (Boot Mode Enable)
Sixteen 16-bit general registers
Flexible instruction set built on 62 basic instruction types
8/16/32-bit data transfer, arithmetic, and logic instructions
Signed and unsigned multiply and divide instructions
Extensive bit manipulation instructions
Bus controller with 8-bit access
3-function refresh controller
DMA controller with short or full address mode
16-bit integrated timer unit (ITU) with 5 channels
Programmable timing pattern controller (TPC)
Watchdog timer
Serial communications interface (SCI) with built-in smart card interface
Eight 10-bit A/D converter channels
Two 8-bit D/A converter channels
Clock pulse generator
Interrupt controller with 37 sources
Seventy input/output pins and eight input-only pins
Available in 100 pin QFP package
The IA64F3048SEC is code compatible with the original Hitachi® H8/300H family of
microcontrollers, with additional security enhancements designed into the device. innovASIC
produces replacement ICs using its MILESTM, or Managed IC Lifetime Extension System, cloning
technology. This technology produces replacement ICs far more complex than "emulation" while
ensuring they are compatible with the original IC. MILESTM captures the design of a clone so it can
be produced even as silicon technology advances. MILESTM also verifies the clone against the
original IC so that even the "undocumented features" are duplicated.
This Advanced Information Sheet contains preliminary information for this the IA64F3048SEC.
The complete data sheet which documents all necessary engineering information about the
IA64F3048SEC including functional and I/O descriptions, electrical characteristics, and applicable
timing will be available when the device nears completion.
Copyright © 2003
The End of Obsolescence®
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