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X1228 Datasheet
Real Time Clock/Calendar/CPU Supervisor with EEPROM

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New Features
Repetitive Alarms &
Temperature Compensation
4K (512 x 8)
X1228
2-WireRTC
Real Time Clock/Calendar/CPU Supervisor with EEPROM
FEATURES
• Real Time Clock/Calendar
— Tracks time in Hours, Minutes, and Seconds
— Day of the Week, Day, Month, and Year
• 2 Polled Alarms (Non-volatile)
— Settable on the Second, Minute, Hour, Day of the
Week, Day, or Month
— Repeat Mode (periodic interrupts)
• Oscillator Compensation on chip
— Internal feedback resistor and compensation
capacitors
— 64 position Digitally Controlled Trim Capacitor
— 6 digital frequency adjustment settings to
±30ppm
• CPU Supervisor Functions
— Power On Reset, Low Voltage Sense
— Watchdog Timer (SW Selectable: 0.25s, 0.75s,
1.75s, off)
• Battery Switch or Super Cap Input
• 512 x 8 Bits of EEPROM
— 64-Byte Page Write Mode
— 8 modes of Block Lock™ Protection
— Single Byte Write Capability
• High Reliability
— Data Retention: 100 years
— Endurance: 100,000 cycles per byte
• 2-Wire™ Interface interoperable with I2C*
— 400kHz data transfer rate
• Frequency Output (SW Selectable: Off, 1Hz,
4096Hz, or 32.768kHz)
• Low Power CMOS
— 1.25µA Operating Current (Typical)
• Small Package Options
— 14-Lead SOIC and 14-Lead TSSOP
APPLICATIONS
• Utility Meters
• HVAC Equipment
• Audio / Video Components
• Set Top Box / Television
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers / PDA
• POS Equipment
• Test Meters / Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial / Medical / Automotive
BLOCK DIAGRAM
32.768kHz
X1
X2
PHZ/IRQ
Select
SCL
SDA
Serial
Interface
Decoder
RESET
Control
Decode
Logic
8
OSC Compensation
Oscillator
Frequency 1Hz
Divider
Timer
Calendar
Logic
Time
Keeping
Registers
(SRAM)
Control/
Registers
(EEPROM)
Status
Registers
(SRAM)
Alarm
Watchdog
Timer
Low Voltage
Reset
Compare
Alarm Regs
(EEPROM)
4K
EEPROM
ARRAY
Battery
Switch
Circuitry
VCC
VBACK
*I2C is a Trademark of Philips.
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X1228 Datasheet
Real Time Clock/Calendar/CPU Supervisor with EEPROM

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X1228
PIN DESCRIPTIONS
14-Pin TSSOP/SOIC
X1
X2
NC
NC
NC
RESET
VSS
1
2
3
4
5
6
7
14 VCC
13 VBACK
12 PHZ/IRQ
11 NC
10 NC
9 SCL
8 SDA
NC = No internal connection
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X1228 Datasheet
Real Time Clock/Calendar/CPU Supervisor with EEPROM

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X1228
PIN ASSIGNMENTS
Pin Number
SOIC/TSSOP Symbol
1 X1
2 X2
6 RESET
7 VSS
8 SDA
9 SCL
12 PHZ/IRQ
13 VBACK
14 VCC
Brief Description
X1. The X1 pin is the input of an inverting amplifier. An external 32.768kHz quartz crystal
is used with the X1228 to supply a timebase for the real time clock. The recommended
crystal is a Citizen CFS206-32.768KDZF. Internal compensation circuitry is included to form
a complete oscillator circuit. Care should be taken in the placement of the crystal and the
layout of the circuit. Plenty of ground plane around the device and short traces to X1 are
highly recommended. See Application section for more recommendations.
X2. The X2 pin is the output of an inverting amplifier. An external 32.768kHz quartz
crystal is used with the X1228 to supply a timebase for the real time clock. The
recommended crystal is a Citizen CFS206-32.768KDZF. Internal compensation circuitry is
included to form a complete oscillator circuit. Care should be taken in the placement of the
crystal and the layout of the circuit. Plenty of ground plane around the device and short traces
to X2 are highly recommended. See Application section for more recommendations.
RESET Output – RESET. This is a reset signal output. This signal notifies a host
processor that the watchdog time period has expired or that the voltage has dropped
below a fixed VTRIP threshold. It is an open drain active LOW output. Recommended
value for the pullup resistor is 5K Ohms. If unused, tie to ground.
VSS.
Serial Data (SDA). SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain or open
collector outputs. The input buffer is always active (not gated).
An open drain output requires the use of a pull-up resistor. The output circuitry controls
the fall time of the output signal with the use of a slope controlled pull-down. The circuit
is designed for 400kHz 2-wire interface speeds.
Serial Clock (SCL). The SCL input is used to clock all data into and out of the device.
The input buffer on this pin is always active (not gated).
Programmable Frequency/Interrupt Output – PHZ/IRQ. This is either an output from
the internal oscillator or an interrupt signal output. It is a CMOS output.
When used as frequency output, this signal has a frequency of 32.768kHz, 4096Hz, 1Hz
or inactive.
When used as interrupt output, this signal notifies a host processor that an alarm has
occurred and an action is required. It is an active LOW output.
The control bits for this function are FO1 and FO0 and are found in address 0011h of the
Clock Control Memory map. See “Programmable Frequency Output Bits—FO1, FO0” on
page 14.
VBACK. This input provides a backup supply voltage to the device. VBACK supplies
power to the device in the event the VCC supply fails. This pin can be connected to a
battery, a Supercap or tied to ground if not used.
VCC.
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X1228 Datasheet
Real Time Clock/Calendar/CPU Supervisor with EEPROM

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X1228
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ................... -65°C to +135°C
Storage Temperature......................... -65°C to +150°C
Voltage on VCC, VBACK and PHZ/IRQ
pin (respect to ground) ............................-0.5V to 7.0V
Voltage on SCL, SDA, X1 and X2
pin (respect to ground) ............... -0.5V to 7.0V or 0.5V
above VCC or VBACK (whichever is higher)
DC Output Current .............................................. 5 mA
Lead Temperature (Soldering, 10 sec) ...............300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute max-
imum rating conditions for extended periods may affect
device reliability.
DC OPERATING CHARACTERISTICS (Temperature = -40°C to +85°C, unless otherwise stated.)
Symbol
VCC
VBACK
VCB
VBC
Parameter
Main Power Supply
Backup Power Supply
Switch to Backup Supply
Switch to Main Supply
Conditions Min Typ Max Unit
2.7 5.5 V
1.8 5.5 V
VBACK -0.2
VBACK
VBACK -0.1
VBACK +0.2
V
V
Notes
OPERATING CHARACTERISTICS
Symbol
ICC1
Parameter
Read Active Supply
Current
ICC2
Program Supply Current
(nonvolatile)
ICC3
IBACK
ILI
ILO
Main Timekeeping
Current
Timekeeping Current –
(Low Voltage Sense
and Watchdog Timer
disabled
Input Leakage Current
Output Leakage Current
Conditions
VCC = 2.7V
VCC = 5.0V
VCC = 2.7V
VCC = 5.0V
VCC = 2.7V
VCC = 5.0V
VBACK = 1.8V
VBACK = 3.3V
Min
VIL Input LOW Voltage
-0.5
VIH
VHYS
VOL1
VOL2
VOH2
Input HIGH Voltage
Schmitt Trigger Input
Hysteresis
Output LOW Voltage for
SDA and RESET
Output LOW Voltage for
PHZ/IRQ
Output HIGH Voltage
for PHZ/IRQ
VCC related level
VCC = 2.7V
VCC = 5.5V
VCC = 2.7V
VCC = 5.5V
VCC = 2.7V
VCC = 5.5V
VCC x 0.7 or
VBACK x 0.7
.05 x VCC or
.05 x VBACK
VCC x 0.7
VCC x 0.7
Typ
1.25
1.5
Max
400
800
2.5
3.0
10
20
Unit
µA
µA
mA
mA
µA
µA
Notes
1, 5, 7, 14
2, 5, 7, 14
3, 7, 8, 14, 15
µA 3, 6, 9, 14, 15
“See Perfor-
µA mance Data”
10
10
VCC x 0.2 or
VBACK x 0.2
VCC + 0.5 or
VBACK + 0.5
µA
µA
V
V
V
10
10
13
13
13
0.4
0.4
VCC x 0.3
VCC x 0.3
V
V
11
11
V 12
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X1228 Datasheet
Real Time Clock/Calendar/CPU Supervisor with EEPROM

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X1228
Notes: (1) The device enters the Active state after any start, and remains active: for 9 clock cycles if the Device Select Bits in the Slave
Address Byte are incorrect or until 200nS after a stop ending a read or write operation.
(2) The device enters the Program state 200nS after a stop ending a write operation and continues for tWC.
(3) The device goes into the Timekeeping state 200nS after any stop, except those that initiate a nonvolatile write cycle; tWC after a
stop that initiates a nonvolatile write cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in
the Slave Address Byte.
(4) For reference only and not tested.
(5) VIL = VCC x 0.1, VIH = VCC x 0.9, fSCL = 400KHz
(6) VCC = 0V
(7) VBACK = 0V
(8) VSDA = VSCL=VCC, Others = GND or VCC
(9) VSDA =VSCL=VBACK, Others = GND or VBACK
(10) VSDA = GND or VCC, VSCL = GND or VCC, VRESET = VCC or GND
(11) IOL = 3.0mA at 5.5V, 1.5mA at 2.7V
(12) IOH = -1.0mA at 5.5V, -0.4mA at 2.7V
(13) Threshold voltages based on the higher of Vcc or Vback.
(14) Using recommended crystal and oscillator network applied to X1 and X2 (25°C).
(15) Typical values are for TA = 25°C
Capacitance TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol
Parameter
Max.
Units
Test Conditions
COUT(1)
CIN(1)
Output Capacitance (SDA, PHZ/IRQ, RESET)
Input Capacitance (SCL)
10
10
pF
pF
VOUT = 0V
VIN = 0V
Notes: (1) This parameter is not 100% tested.
(2) The input capacitance between x1 and x2 pins can be varied between 5pF and 19.75pF by using analog trimming registers
AC CHARACTERISTICS
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Levels
Output Load
VCC x 0.1 to VCC x 0.9
10ns
VCC x 0.5
Standard Output Load
Figure 18. Standard Output Load for testing the device with VCC = 5.0V
Equivalent AC Output Load Circuit for VCC = 5V
5.0V
5.0V
SDA
1533
For VOL= 0.4V
and IOL = 3 mA
100pF
PHZ/IRQ
1316
806
100pF
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