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X20C17PM-55 Datasheet
High Speed AUTOSTORE NOVRAM

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APPLICATION NOTE
AVA I L A B L E
X20C17 AN56
16K X20C17
High Speed AUTOSTORE™ NOVRAM
2K x 8 Bit
FEATURES
24-Pin Standard SRAM DIP Pinout
Fast Access Time: 35ns, 45ns, 55ns
High Reliability
—Endurance: 1,000,000 Nonvolatile Store
Operations
—Retention: 100 Years Minimum
AUTOSTORE™ NOVRAM
—Automatically Stores SRAM Data Into the
E2PROM Array When VCC Low Threshold is
Detected
—E2PROM Data Automatically Recalled Into
RAM Upon Power-up
Low Power CMOS
—Standby: 250µA
Infinite E2PROM Array Recall, and RAM Read
and Write Cycles
DESCRIPTION
The Xicor X20C17 is a 2K x 8 NOVRAM featuring a high-
speed static RAM overlaid bit-for-bit with a nonvolatile
electrically erasable PROM (E2PROM) and the
AUTOSTORE feature which automatically saves the
RAM contents to E2PROM at power-down. The X20C17
is fabricated with advanced CMOS floating gate technol-
ogy to achieve high speed with low power and wide
power-supply margin. The X20C17 features a compat-
ible JEDEC approved byte-wide memory pinout for
industry standard SRAMs.
The NOVRAM design allows data to be easily trans-
ferred from RAM to E2PROM (store) and E2PROM to
RAM (recall). The store operation is completed in 2.5ms
or less. An automatic array recall operation reloads the
contents of the E2PROM into RAM upon power-up.
Xicor NOVRAMS are designed for unlimited write
operations to RAM, either from the host or recalls from
E2PROM, and a minimum 1,000,000 store operations to
the E2PROM. Data retention is specified to be greater
than 100 years.
PIN CONFIGURATION
PLASTIC
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1 24
2 23
3 22
4 21
5 20
6 19
X20C17
7 18
8 17
9 16
10 15
11 14
12 13
VCC
A8
A9
WE
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
2015 ILL F02.1
AUTOSTORE™ NOVRAM is a trademark of Xicor, Inc.
©Xicor, Inc. 1992, 1995 Patents Pending
2015-2.5 8/1/97 T1/C0/D0 SH
1
Characteristics subject to change without notice


X20C17PM-55 Datasheet
High Speed AUTOSTORE NOVRAM

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X20C17
PIN DESCRIPTIONS
Addresses (A0–A10)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consumption
is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read and recall operations. Output
Enable LOW disables a store operation regardless of
the state of CE, WE.
Data In/Data Out (I/O0–I/O7)
Data is written to or read from the X20C17 through the
I/O pins. The I/O pins are placed in the high impedance
state when either CE or OE is HIGH.
Write Enable (WE)
The Write Enable input controls the writing of data to the
static RAM.
FUNCTIONAL DIAGRAM
PIN NAMES
Symbol
A0–A10
I/O0–I/O7
WE
CE
OE
VCC
VSS
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Ground
2015 PGM T01
A3–A8
CE
OE
WE
A0–A2
A9–A10
CONTROL
LOGIC
VCC SENSE
EEPROM ARRAY
ROW
SELECT
HIGH SPEED
2K x 8
SRAM
ARRAY
COLUMN
SELECT
&
I/OS
I/O0–I/O7
2
2015 FHD F01.1


X20C17PM-55 Datasheet
High Speed AUTOSTORE NOVRAM

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X20C17
DEVICE OPERATION
The CE, OE, and WE inputs control the X20C17 opera-
tion. The X20C17 byte-wide NOVRAM uses a
2-line control architecture to eliminate bus contention in
a system environment. The I/O bus will be in a high
impedance state when either OE or CE is HIGH.
RAM Operations
RAM read and write operations are performed as they
would be with any static RAM. A read operation requires
CE and OE to be LOW. A write operation requires CE
and WE to be LOW. There is no limit to the number of
read or write operations performed to the RAM portion
of the X20C17.
Memory Transfer Operations
There are two memory transfer operations: a recall
operation whereby the data stored in the E2PROM array
is transferred to the RAM array; and a store operation
which causes the entire contents of the RAM array to be
stored in the E2PROM array.
Recall operations are performed automatically upon
power-up.
Store operations are performed automatically upon
power-down. The store operation take a maximum of
2.5ms.
Write Protection
The X20C17 supports two methods of protecting the
nonvolatile data.
—If after power-up no RAM write operations have
occured, no AUTOSTORE operation can be initiated.
—VCC Sense – All functions are inhibited when VCC is
3V typical.
SYMBOL TABLE
The following symbol table provides a key to under-
standing the conventions used in the device timing
diagrams. The diagrams should be used in conjunction
with the device timing specifications to determine actual
device operation and performance, as well as device
suitability for user’s application.
WAVEFORM INPUTS
OUTPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
3


X20C17PM-55 Datasheet
High Speed AUTOSTORE NOVRAM

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X20C17
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias .................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to VSS ....................................... –1V to +7V
D.C. Output Current ........................................... 10mA
Lead Temperature (Soldering, 10 seconds) ...... 300°C
RECOMMENDED OPERATING CONDITIONS
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any conditions other than those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
Temperature
Commercial
Industrial
Military
Min.
0°C
–40°C
–55°C
Max.
+70°C
+85°C
+125°C
2015 PGM T02.1
Supply Voltage
X20C17
Limits
4.5V to 5.25V
2015 PGM T03.1
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Symbol
Parameter
lCC1 VCC Current (Active)
ICC2(2)
ISB1
ISB2
ILI
ILO
VIL(1)
VIH(1)
VOL
VOH
VCC Current During
AUTOSTORE
VCC Standby Current
(TTL Input)
VCC Standby Current
(CMOS Input)
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Min.
Limits
Max.
100
Units
mA
2.5 mA
10 mA
250 µA
10 µA
10 µA
–1 0.8
V
2 VCC + 1 V
0.4 V
2.4 V
Test Conditions
WE = VIH, CE = OE = VIL
Address Inputs = 0.4V/2.4V Levels
@ f = 20MHz, All I/Os = Open
All I/Os = Open
All Inputs = VIH, All I/Os = Open
All Inputs = VCC – 0.3V
All I/Os = Open
VIN = VSS to VCC
VOUT = VSS to VCC, CE = VIH
IOL = 4mA
IOH = –4mA
2015 PGM T04.3
POWER-UP TIMING
Symbol
tPUR(2)
tPUW(2)
Parameter
Power-Up to RAM Operation
Power-Up to Nonvolatile Operation
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V.
Symbol
Test
CI/O(2)
CIN(2)
Input/Output Capacitance
Input Capacitance
Notes: (1) VIL min. and VIH max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
Max.
10
6
Max.
100
5
Units
pF
pF
Units
µs
ms
2015 PGM T05
Conditions
VI/O = 0V
VIN = 0V
2015 PGM T06.2
4


X20C17PM-55 Datasheet
High Speed AUTOSTORE NOVRAM

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X20C17
ENDURANCE AND DATA RETENTION
Parameter
Endurance
Store Cycles
Data Retention
Min.
100,000
1,000,000
100
MODE SELECTION
CE WE OE
HXX
L HL
L LH
L LH
L LL
L HH
Mode
Not Selected
Read RAM
Write “1” RAM
Write “0” RAM
Not Allowed
No Operation
Units
Data Changes Per Bit
Store Cycles
Years
2015 PGM T07.1
I/O
Output High Z
Output Data
Input Data High
Input Data Low
Output High Z
Output High Z
Power
Standby
Active
Active
Active
Active
Active
2015 PGM T09
EQUIVALENT A.C. LOAD CIRCUIT
5V
893
OUTPUT
347
30pF
2015 FHD F04
A.C. CONDITIONS OF TEST
Input Pulse Levels
Input Rise and
Fall Times
Input and Output
Timing Levels
0V to 3V
5ns
1.5V
2015 PGM T08.1
5


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