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AD5341 Datasheet
Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs

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2.5 V to 5.5 V, 115 μA, Parallel Interface
Single Voltage-Output 8-/10-/12-Bit DACs
AD5330/AD5331/AD5340/AD5341
FEATURES
GENERAL DESCRIPTION
AD5330: single 8-bit DAC in 20-lead TSSOP
AD5331: single 10-bit DAC in 20-lead TSSOP
AD5340: single 12-bit DAC in 24-lead TSSOP
AD5341: single 12-bit DAC in 20-lead TSSOP
Low power operation: 115 μA @ 3 V, 140 μA @ 5 V
Power-down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin
2.5 V to 5.5 V power supply
Double-buffered input logic
Guaranteed monotonic by design over all codes
Buffered/unbuffered reference input options
Output range: 0 V to VREF or 0 V to 2 × VREF
Power-on reset to 0 V
Simultaneous update of DAC outputs via LDAC pin
Asynchronous CLR facility
Low power parallel data interface
On-chip rail-to-rail output buffer amplifiers
Temperature range: −40°C to +105°C
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Industrial process control
The AD5330/AD5331/AD5340/AD53411 are single 8-/10-/12-
bit DACs. They operate from a 2.5 V to 5.5 V supply consuming
just 115 μA at 3 V and feature a power-down mode that further
reduces the current to 80 nA. The devices incorporate an on-chip
output buffer that can drive the output to both supply rails, but
the AD5330, AD5340, and AD5341 allow a choice of buffered
or unbuffered reference input.
The AD5330/AD5331/AD5340/AD5341 have a parallel
interface. CS selects the device and data is loaded into the
input registers on the rising edge of WR.
The GAIN pin allows the output range to be set at 0 V to VREF or
0 V to 2 × VREF.
Input data to the DACs is double-buffered, allowing simultane-
ous update of multiple DACs in a system using the LDAC pin.
An asynchronous CLR input is also provided, which resets the
contents of the input register and the DAC register to all zeros.
These devices also incorporate a power-on reset circuit that
ensures that the DAC output powers on to 0 V and remains
there until valid data is written to the device.
The AD5330/AD5331/AD5340/AD5341 are available in thin
shrink small outline packages (TSSOP).
1 Protected by U.S. Patent Number 5,969,657.
FUNCTIONAL BLOCK DIAGRAM
VREF
3
VDD
12
POWER-ON
RESET
AD5330
BUF 1
GAIN 8
DB.. 7 20
DB0 13
CS 6
WR 7
CLR 9
LDAC 10
INPUT
REGISTER
DAC
REGISTER
8-BIT
DAC
BUFFER
4 VOUT
RESET
POWER-DOWN
LOGIC
Figure 1. AD5330
11 5
PD GND
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2000–2008 Analog Devices, Inc. All rights reserved.


AD5341 Datasheet
Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs

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AD5330/AD5331/AD5340/AD5341
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 4
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Terminology .................................................................................... 11
Typical Performance Characteristics ........................................... 13
Theory of Operation ...................................................................... 17
Digital-to-Analog Section ......................................................... 17
Resistor String ............................................................................. 17
DAC Reference Input................................................................. 17
Output Amplifier........................................................................ 17
Parallel Interface ............................................................................. 18
REVISION HISTORY
2/08—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Table 4.......................................................................... 16
Replaced Driving VDD from the Reference Voltage Section ..... 21
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 25
4/00—Revision 0: Initial Version
Double-Buffered Interface ........................................................ 18
Clear Input (CLR) ...................................................................... 18
Chip Select Input (CS)............................................................... 18
Write Input (WR) ....................................................................... 18
Load DAC Input (LDAC).......................................................... 18
High-Byte Enable Input (HBEN)............................................. 18
Power-On Reset.......................................................................... 18
Power-Down Mode ........................................................................ 19
Suggested Databus Formats .......................................................... 20
Applications Information .............................................................. 21
Typical Application Circuits ..................................................... 21
Driving VDD From the Reference Voltage ............................... 21
Bipolar Operation Using the AD5330/AD5331/
AD5340/AD5341......................................................................... 21
Decoding Multiple AD5330/AD5331/ AD5340/AD5341 .... 21
Programmable Current Source ................................................ 22
Power Supply Bypassing and Grounding................................ 22
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 25
Rev. A | Page 2 of 28


AD5341 Datasheet
Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs

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AD5330/AD5331/AD5340/AD5341
SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VREF = 2 V, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter1
DC PERFORMANCE3, 4
AD5330
Resolution
Relative Accuracy
Differential Nonlinearity
AD5331
Resolution
Relative Accuracy
Differential Nonlinearity
AD5340/AD5341
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
Lower Deadband5
Upper Deadband
Offset Error Drift6
Gain Error Drift6
DC Power Supply Rejection Ratio6
DAC REFERENCE INPUT6
VREF Input Range
VREF Input Impedance
Reference Feedthrough
OUTPUT CHARACTERISTICS6
Minimum Output Voltage4, 7
Maximum Output Voltage4, 7
DC Output Impedance
Short-Circuit Current
Power-Up Time
LOGIC INPUTS6
Input Current
Input Low Voltage, VIL
Input High Voltage, VIH
Pin Capacitance
B Version2
Min Typ
Max Unit
Conditions/Comments
8
±0.15
±0.02
±1
±0.25
Bits
LSB
LSB
Guaranteed monotonic by design over all codes
10
±0.5
±0.05
Bits
±4 LSB
±0.5 LSB
Guaranteed monotonic by design over all codes
12
±2
±0.2
±0.4
±0.15
10
10
−12
−5
−60
Bits
±16 LSBs
±1 LSB
Guaranteed monotonic by design over all codes
±3 % of FSR
±1 % of FSR
60 mV
Lower deadband exists only if offset error is negative
60 mV
VDD = 5 V; upper deadband exists only if VREF = VDD
ppm of FSR/°C
ppm of FSR/°C
dB ΔVDD = ±10%
1
0.25
>10
180
90
−90
VDD V
VDD V
dB
Buffered reference (AD5330, AD5340, and AD5341)
Unbuffered reference
Buffered reference (AD5330, AD5340, and AD5341)
Unbuffered reference; gain = 1, input impedance = RDAC
Unbuffered reference; gain = 2, input impedance = RDAC
Frequency = 10 kHz
0.001
VDD− 0.001
0.5
25
15
2.5
5
V min
V max
Ω
mA
mA
μs
μs
Rail-to-rail operation
VDD = 5 V
VDD = 3 V
Coming out of power-down mode; VDD = 5 V
Coming out of power-down mode; VDD = 3 V
±1
2.4
2.1
2.0
3
μA
0.8 V
0.6 V
0.5 V
V
V
V
pF
VDD = 5 V ± 10%
VDD = 3 V ± 10%
VDD = 2.5 V
VDD = 5 V ± 10%
VDD = 3 V ± 10%
VDD = 2.5 V
Rev. A | Page 3 of 28


AD5341 Datasheet
Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs

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AD5330/AD5331/AD5340/AD5341
Parameter1
POWER REQUIREMENTS
VDD
IDD (Normal Mode)
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.6 V
IDD (Power-Down Mode)
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.6 V
B Version2
Min Typ
Max Unit
2.5 5.5 V
140 250 μA
115 200 μA
0.2 1 μA
0.08 1 μA
Conditions/Comments
DACs active and excluding load currents. Unbuffered
Reference, VIH = VDD, VIL = GND
IDD increases by 50 μA at VREF > VDD − 100 mV.
In buffered mode, extra current is (5 + VREF/RDAC) μA,
where RDAC is the resistance of the resistor string.
1 See the Terminology section.
2 Temperature range: B Version: −40°C to +105°C; typical specifications are at 25°C.
3 Linearity is tested using a reduced code range: AD5330 (Code 8 to Code 255); AD5331 (Code 28 to Code 1023); AD5340/AD5341 (Code 115 to Code 4095).
4 DC specifications tested with output unloaded.
5 This corresponds to x codes. x = deadband voltage/LSB size.
6 Guaranteed by design and characterization, not production tested.
7 For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD and offset plus
gain error must be positive.
AC CHARACTERISTICS1
VDD = 2.5 V to 5.5 V. RL = 2 kΩ to GND, CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter2
Output Voltage Settling Time
AD5330
AD5331
AD5340
AD5341
Slew Rate
Major Code Transition Glitch Energy
Digital Feedthrough
Multiplying Bandwidth
Total Harmonic Distortion
B Version3
Min Typ Max Unit Conditions/Comments
VREF = 2 V; see Figure 29
68
μs ¼ scale to ¾ scale change (0x40 to 0xC0)
79
μs ¼ scale to ¾ scale change (0x100 to 0x300)
8 10 μs ¼ scale to ¾ scale change (0x400 to 0xC00)
8 10 μs ¼ scale to ¾ scale change (0x400 to 0xC00)
0.7 V/μs
6 nV/s 1 LSB change around major carry
0.5 nV/s
200 kHz VREF = 2 V ± 0.1 V p-p; unbuffered mode
−70 dB VREF = 2.5 V ± 0.1 V p-p; frequency = 10 kHz
1 Guaranteed by design and characterization, not production tested.
2 See the Terminology section.
3 Temperature range: B Version: −40°C to +105°C; typical specifications are at 25°C.
Rev. A | Page 4 of 28


AD5341 Datasheet
Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs

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AD5330/AD5331/AD5340/AD5341
TIMING CHARACTERISTICS1, 2, 3
VDD = 2.5 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
Limit at TMIN, TMAX
0
0
20
5
4.5
5
5
4.5
5
4.5
20
20
50
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Condition/Comments
CS to WR setup time.
CS to WR hold time.
WR pulse width.
Data, GAIN, BUF, HBEN setup time.
Data, GAIN, BUF, HBEN hold time.
Synchronous mode; WR falling to LDAC falling.
Synchronous mode; LDAC falling to WR rising.
Synchronous mode; WR rising to LDAC rising.
Asynchronous mode; LDAC rising to WR rising.
Asynchronous mode; WR rising to LDAC falling.
LDAC pulse width.
CLR pulse width.
Time between WR cycles.
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3 See Figure 2.
CS
WR
DATA,
GAIN,
BUF,
HBEN
LDAC1
LDAC2
t1 t2
t3
t4 t5
t13
t6 t7 t8
t9 t10
t11
CLR
t12
NOTES:
1SYNCHRONOUS LDAC UPDATE MODE
2ASYNCHRONOUS LDAC UPDATE MODE
Figure 2. Parallel Interface Timing Diagram
Rev. A | Page 5 of 28


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