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AD6640 Datasheet
12-Bit/ 65 MSPS IF Sampling A/D Converter

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a
FEATURES
65 MSPS Minimum Sample Rate
80 dB Spurious-Free Dynamic Range
IF-Sampling to 70 MHz
710 mW Power Dissipation
Single +5 V Supply
On-Chip T/H and Reference
Twos Complement Output Format
3.3 V or 5 V CMOS-Compatible Output Levels
APPLICATIONS
Cellular/PCS Base Stations
Multichannel, Multimode Receivers
GPS Anti-Jamming Receivers
Communications Receivers
Phased Array Receivers
12-Bit, 65 MSPS
IF Sampling A/D Converter
AD6640
FUNCTIONAL BLOCK DIAGRAM
AIN
AIN
VREF
ENCODE
ENCODE
AVCC
DVCC
BUF TH1
TH2
TH3 A
ADC
+2.4V
REFERENCE
INTERNAL
TIMING
GND
ADC
DAC
AD6640
7
6
DIGITAL ERROR CORRECTION LOGIC
MSB
LSB
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PRODUCT DESCRIPTION
The AD6640 is a high speed, high performance, low power,
monolithic 12-bit analog-to-digital converter. All necessary
functions, including track-and-hold (T/H) and reference are
included on-chip to provide a complete conversion solution.
The AD6640 runs on a single +5 V supply and provides CMOS-
compatible digital outputs at 65 MSPS.
Specifically designed to address the needs of multichannel,
multimode receivers, the AD6640 maintains 80 dB spurious-
free dynamic range (SFDR) over a bandwidth of 25 MHz.
Noise performance is also exceptional; typical signal-to-noise
ratio is 68 dB.
The AD6640 is built on Analog Devices’ high speed complemen-
tary bipolar process (XFCB) and uses an innovative multipass
architecture. Units are packaged in a 44-terminal Plastic Thin
Quad Flatpack (TQFP) specified from –40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate is 65 MSPS.
2. Fully differential analog input stage specified for frequencies
up to 70 MHz; enables “IF Sampling.”
3. Low power dissipation: 710 mW off a single +5 V supply.
4. Digital outputs may be run on +3.3 V supply for easy inter-
face to digital ASICs.
5. Complete Solution: reference and track-and-hold.
6. Packaged in small, surface mount, plastic 44-terminal TQFP.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998

AD6640 Datasheet
12-Bit/ 65 MSPS IF Sampling A/D Converter

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AD6640–SPECIFICATIONS
DC SPECIFICATIONS (AVCC = +5 V, DVCC = +3.3 V; TMIN = –40؇C, TMAX = +85؇C)
Parameter
Temp
Test
Level
AD6640AST
Min Typ
Max
Units
RESOLUTION
12 Bits
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)1
Integral Nonlinearity (INL)1
+25°C
Full
Full
+25°C
Full
I
VI
VI
I
V
GUARANTEED
–10 3.5
–10 4.0
–1.0 ± 0.5
± 1.25
+10
+10
+1.5
mV
% FS
LSB
LSB
TEMPERATURE DRIFT
Offset Error
Gain Error
Full V
Full V
50
100
ppm/°C
ppm/°C
POWER SUPPLY REJECTION (PSRR)
REFERENCE OUT (VREF)2
ANALOG INPUTS (AIN, AIN)3
Analog Input Common-Mode Range4
Differential Input Voltage Range
Differential Input Resistance
Differential Input Capacitance
Full
Full
Full
Full
Full
+25°C
V
V
V
V
IV
V
0.7
± 0.5
2.4
VREF ± 0.05
2.0
0.9
1.5
1.1
mV/V
V
V
V p-p
k
pF
POWER SUPPLY
Supply Voltage
AVCC
DVCC
Supply Current
IAVCC (AVCC = 5.0 V)
IDVCC (DVCC = 3.3 V)
Full VI
4.75
5.0
5.25 V
Full VI
3.0
3.3 5.25 V
Full VI
Full VI
135 160
10 20
mA
mA
POWER CONSUMPTION
Full VI
710 865
mW
NOTES
1ENCODE = 20 MSPS
2If VREF is used to provide a dc offset to other circuits, it should first be buffered.
3The AD6640 is designed to be driven differentially. Both AIN and AIN should be driven at levels VREF ± 0.5 volts. The input signals should be 180 degrees out of phase to
produce a 2 V p-p differential input signal. See Driving the Analog Inputs section for more details.
4Analog input common-mode range specifies the offset range the analog inputs can tolerate in dc-coupled applications (see Figure 35 for more detail).
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS (AVCC = +5 V, DVCC = +3.3 V; TMIN = –40؇C, TMAX = +85؇C)
Parameter
Temp
Test
Level
AD6640AST
Min Typ
Max
Units
LOGIC INPUTS (ENC, ENC)1
Encode Input Common-Mode Range2
Differential Input Voltage
Single-Ended Encode
Logic Compatibility3
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current (VINH = 5 V)
Logic “0” Current (VINL = 0 V)
Input Capacitance
Full
Full
Full
Full
Full
Full
+25°C
IV
IV
VI
VI
VI
VI
V
0.2
0.4
2.0
0
500
–400
TTL/CMOS
650
–320
2.5
2.2
10
5.0
0.8
800
–200
V
V p-p
V p-p
V
V
µA
µA
pF
LOGIC OUTPUTS (D11–D0)4
Logic Compatibility
Logic “1” Voltage (DVCC = +3.3 V)
Logic “0” Voltage (DVCC = +3.3 V)
Logic “1” Voltage (DVCC = +5.0 V)
Logic “0” Voltage (DVCC = +5.0 V)
Output Coding
Full VI
Full VI
Full IV
Full IV
CMOS
2.8 DVCC – 0.2
0.2
4.5 DVCC – 0.3
0.35
Twos Complement
0.5
0.5
V
V
V
V
NOTES
1Best dynamic performance is obtained by driving ENC and ENC differentially. See Encoding the AD6640 section for more details. Performance versus ENC/ENC power is
shown in Figure 18 under Typical Performance Characteristics.
2For dc-coupled applications, Encode Input Common-Mode Range specifies the common-mode range the encode inputs can tolerate when driven differentially by minimum
differential input voltage of 0.4 V p-p. For differential input voltage swings greater than 0.4 V p-p, the common-mode range will change. The minimum value insures that the
input voltage on either encode pin does not go below 0 V. The maximum value insures that the input voltage on either encode pin does not go below 2.0 V or above AVCC (e.g.,
for a differential input swing of 0.8 V, the min and max common-mode specs become 0.4 V and 2.4 V respectively).
3ENC or ENC may be driven alone if desired, but performance will likely be degraded. Logic Compatibility specifications are provided to show that TTL or CMOS clock sources
will work. When driving only one encode input, bypass the complementary input to GND with 0.01 µF.
4Digital output load is one LCX gate.
Specifications subject to change without notice.
–2– REV. 0

AD6640 Datasheet
12-Bit/ 65 MSPS IF Sampling A/D Converter

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AD6640
SWITCHING SPECIFICATIONS1
(AVCC = +5 V, DVCC = +3.3 V; ENCODE & ENCODE = 65 MSPS; TMIN = –40؇C, TMAX = +85؇C)
Parameter (Conditions)
Temp
Test
Level
AD6640AST
Min Typ Max
Units
Maximum Conversion Rate
Minimum Conversion Rate2
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
ENCODE Pulsewidth High3
ENCODE Pulsewidth Low
Output Delay (tOD) DVCC +3.3 V/5.0 V4
Full
Full
+25°C
+25°C
+25°C
+25°C
Full
VI 65
MSPS
IV 6.5 MSPS
V 400 ps
V 0.3 ps rms
IV 6.5
ns
IV 6.5
ns
IV 8.5 10.5 12.5 ns
NOTES
1All switching specifications tested by driving ENCODE and ENCODE differentially.
2A plot of Performance vs. Encode is shown in Figure 16 under Typical Performance Characteristics.
3A plot of Performance vs. Duty Cycle (Encode = 65 MSPS) is shown in Figure 17 under Typical Performance Characteristics.
4Outputs driving one LCX gate. Delay is measured from differential crossing of ENC, ENC to the time when all output data bits are within valid logic levels.
Specifications subject to change without notice.
AC SPECIFICATIONS1 (AVCC = +5 V, DVCC = +3.3 V; ENCODE & ENCODE = 65 MSPS; TMIN = –40؇C, TMAX = +85؇C)
Parameter (Conditions)
Temp
Test
Level
AD6640AST
Min Typ
Max
Units
SNR
Analog Input
@ –1 dBFS
2.2 MHz
15.5 MHz
31.0 MHz
69.0 MHz
+25°C
V
68
+25°C
I
64 67.7
+25°C
V
67.5
+25°C
V
66
dB
dB
dB
dB
SINAD
Analog Input
@ –1 dBFS
2.2 MHz
15.5 MHz
31.0 MHz
69.0 MHz
Worst Harmonic2 (2nd or 3rd)
Analog Input 2.2 MHz
@ –1 dBFS 15.5 MHz
31.0 MHz
69.0 MHz
Worst Harmonic2 (4th or Higher)
Analog Input 2.2 MHz
@ –1 dBFS 15.5 MHz
31.0 MHz
69.0 MHz
Multitone SFDR (w/Dither)3
Eight Tones @ –20 dBFS
Two-Tone IMD Rejection4
F1, F2 @ –7 dBFS
Analog Input Bandwidth5
+25°C
V
68
+25°C
I
63.5 67.2
+25°C
V
67.0
+25°C
V
65.5
+25°C
V
80
+25°C
I
74 80
+25°C
V
79.5
+25°C
V
78.5
+25°C
V
85
+25°C
I
74 85
+25°C
V
85
+25°C
V
84
Full V
90
Full
+25°C
V
V
80
300
dB
dB
dB
dB
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBFS
dBc
MHz
NOTES
1All ac specifications tested by driving ENCODE and ENCODE differentially.
2For a single test tone at –1 dBFS, the worst case spectral performance is typically limited by the direct or aliased 2nd or 3rd harmonic. If a system is designed such
that the 2nd and 3rd harmonics fall out-of-band, overall performance in the band of interest is typically improved by 5 dB. Worst Harmonic (4th or Higher) includes
4th and higher order harmonics and all other spurious components. Reference Figure 12 for more detail.
3See Overcoming Static Nonlinearities with Dither section for details on improving SFDR performance. To measure SFDR, eight tones from 14 MHz to 18 MHz
(0.5 MHz spacing) are swept from –20 dBFS to –90 dBFS. An open channel at 16 MHz is used to monitor SFDR.
4F1 = 14.9 MHz, F2 = 16 MHz.
5Specification is small signal bandwidth. Plots of Performance versus Analog Input Frequency are shown in Figures 10, 11 and 12. Sampling wide bandwidths
(5 MHz–15 MHz) should be limited to 70 MHz center frequency.
Specifications subject to change without notice.
REV. 0
–3–


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