AD671 Datasheet
Monolithic 12-Bit 2 MHz A/D Converter

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a
Monolithic 12-Bit
2 MHz A/D Converter
AD671
FEATURES
FUNCTIONAL BLOCK DIAGRAM
12-Bit Resolution
24-Pin “Skinny DIP” Package
Conversion Time: 500 ns max—AD671J/K/S-500
AIN BPO/UPO ENCODE REF IN VCC ACOM VEE VLOGIC
20 21
16 19 23 22 24 17
DCOM
18
Conversion Time: 750 ns max—AD671J/K/S-750
Low Power: 475 mW
RANGE
SELECT
X4
Unipolar (0 V to +5 V, 0 V to +10 V) and Bipolar Input
COARSE
8-BIT
Ranges (؎5 V)
Twos Complement or Offset Binary Output Data
Out-of-Range Indicator
MIL-STD-883 Compliant Versions Available
OBSPRODUCT DESCRIPTION
OThe AD671 is a high speed monolithic 12-bit A/D converter
offering conversion rates of up to 2 MHz (500 ns conversion
Ltime). The combination of a merged high speed bipolar/CMOS
Eprocess and a novel architecture results in a combination of
speed and power consumption far superior to previously avail-
TEable hybrid implementations. Additionally, the greater reliability
3-BIT
FLASH
DAC
3-BIT
FLASH
DAC
4-BIT
FLASH
LADDER
MATRIX
3
AD671
3
CORRECTION LOGIC
4
8
LATCHES
FINE
4-BIT
FLASH
4
12
14 13
OTR MSB
12 1
BIT1-12
15
DAV
PRODUCT HIGHLIGHTS
1. The AD671 offers a single chip 2 MHz analog-to-digital
conversion function in a space saving 24-pin DIP.
2. Input signal ranges are 0 V to +5 V and 0 V to +10 V unipo-
lar, and –5 V to +5 V bipolar, selected by pin strapping. In-
put resistance is 1.5 k. Power supplies are +5 V and –5 V,
and typical power consumption is less than 500 mW.
of monolithic construction offers improved system reliability
and lower costs than hybrid designs.
3. The external +5 V reference can be chosen to suit the dc ac-
The AD671 uses a subranging flash conversion technique, with
curacy and temperature drift requirements of the application.
digital error correction for possible errors introduced in the first 4. Output data is available in unipolar, bipolar offset or bipolar
part of the conversion cycle. An on-chip timing generator pro-
twos complement binary format.
vides strobe pulses for each of the four internal flash cycles and
assures adequate settling time for the interflash residue ampli-
fier. A single ENCODE pulse is used to control the converter.
The performance of the AD671 is made possible by using high
speed, low noise bipolar circuitry in the linear sections and low
power CMOS for the logic sections. Analog Devices’ ABCMOS-1
process provides both high speed bipolar and 2-micron CMOS
5. An OUT OF RANGE output bit indicates when the input
signal is beyond the AD671’s input range.
6. The AD671 is available in versions compliant with the MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD671/883B data sheet for detailed
specifications.
devices on a single chip. Laser trimmed thin-film resistors are
used to provide accuracy and temperature stability.
The AD671 is available in two conversion speeds and perfor-
mance grades. The AD671J and K grades are specified for op-
eration over the 0°C to +70°C temperature range. The AD671S
grades are specified for operation over the –55°C to +125°C
temperature range. All grades are available in a 0.300 inch wide
24-pin ceramic DIP. The J and K grades are also available in a
24-pin plastic DIP.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703


AD671 Datasheet
Monolithic 12-Bit 2 MHz A/D Converter

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AD671–SPECIFICATIONS
DC SPECIFICATIONS (TMIN to TMAX with VCC = +5 V ؎ 5%, VLOGIC = +5 V ؎10%, VEE = –5 V ؎ 5%, VREF = +5.000 V,
unless otherwise noted)
Parameter
AD671J/S-500
Min Typ Max
AD671K-500
Min Typ Max
Units
RESOLUTION
12
12
Bits
ACCURACY (+25°C)
Integral Nonlinearity (INL)
TMIN to TMAX
Differential Nonlinearity (DNL)
؎4 ؎2 LSB
TMIN to TMAX
No Missing Codes
10
10 Bits Guaranteed
11
11 Bits Guaranteed
Bits
Unipolar Offsetl
؎4 ؎4 LSB
Bipolar Zerol
Gain Error2
TEMPERATURE COEFFICIENTS3
Unipolar Offset
Bipolar Zero
Gain Error
OANALOG INPUT
BInput Ranges
Bipolar
SUnipolar
OInput Resistance
L10 Volt Range
E5 Volt Range
Input Capacitance
TEReference Input Resistance
–5
0
0
1.0
0.5
2.4
؎10
0.1 0.25
؎10
؎15
؎20
+5
+5
+10
1.5 2.0
0.75 1.0
10
3.5 4.7
–5
0
0
1.0
0.5
2.4
؎10
0.1 0.25
؎10
؎15
؎20
+5
+5
+10
1.5 2.0
0.75 1.0
10
3.5 4.7
LSB
% FSR
ppm/°C
ppm/°C
ppm/°C
Volts
Volts
Volts
k
k
pF
k
POWER SUPPLIES
Power Supply Rejection4
VCC (+5 V ± 0.25 V)
VLOGIC (+5 V ± 0.5 V)
VEE (–5 V ± 0.25 V)
Operating Voltages
VCC
VLOGIC
VEE
Operating Current
ICC
ILOGIC5
IEE
+4.75
+4.5
–5.25
46
3
46
؎1
؎1
؎1
+5.25
+5.5
–4.75
56
6
56
+4.75
+4.5
–5.25
46
3
46
؎1
؎1
؎1
+5.25
+5.5
–4.75
56
6
56
LSB
LSB
LSB
Volts
Volts
Volts
mA
mA
mA
POWER CONSUMPTION
475 621
475 621
mW
TEMPERATURE RANGE
Specified (J/K)
Specified (S)
0
–55
+70
+125
0
+70 °C
°C
NOTES
1Adjustable to zero with external potentiometers. See Offset/Gain Calibration section for additional information.
2Full-scale range (FSR) is 5 V for the 0 V to 5 V range and 10 V for the 0 V to 10 V and –5 V to +5 V ranges.
325°C to TMIN and 25°C to TMAX.
4Change in gain error as a function of the dc supply voltage.
5Tested under static conditions. See Figure 12 for typical curves of ILOGIC vs. Conversion Rate and Output Loading.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all devices at final electrical test with worst case supply voltages at 0, +25 °C and +70°C. Results from those tests are
used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested.
–2– REV. B


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Monolithic 12-Bit 2 MHz A/D Converter

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AD671
DC SPECIFICATIONS (TMIN to TMAX with VCC = +5 V ؎ 5%, VLOGIC = +5 V ؎ 10%, VEE = –5 V ؎ 5%, VREF = +5.000 V,
unless otherwise noted)
Parameter
AD671J/S-750
Min Typ Max
AD671K-750
Min Typ Max
Units
RESOLUTION
12
12
Bits
ACCURACY (+25°C)
Integral Nonlinearity (INL)
TMIN to TMAX (J)
TMIN to TMAX (S)
؎2
؎2.5
؎1.5
LSB
LSB
Differential Nonlinearity (DNL)
TMIN to TMAX
11
12
Bits
No Missing Codes
11 Bits Guaranteed
12 Bits Guaranteed
Unipolar Offsetl
Bipolar Zerol
Gain Error2
TEMPERATURE COEFFICIENTS3
Unipolar Offset
OBipolar Zero
Gain Error
BANALOG INPUT
SInput Ranges
Bipolar
OUnipolar
LInput Resistance
E10 Volt Range
5 Volt Range
TEInput Capacitance
–5
0
0
1.0
0.5
؎4
؎10
0.1 0.25
؎10
؎15
؎20
+5
+5
+10
1.5 2.0
0.75 1.0
10
–5
0
0
1.0
0.5
؎4
؎10
0.1 0.25
؎10
؎15
؎20
+5
+5
+10
1.5 2.0
0.75 1.0
10
LSB
LSB
% FSR
ppm/°C
ppm/°C
ppm/°C
Volts
Volts
Volts
k
k
pF
Reference Input Resistance
2.4 3.5 4.7 2.4 3.5 4.7
k
POWER SUPPLIES
Power Supply Rejection4
VCC (+5 V ± 0.25 V)
VLOGIC (+5 V ± 0.5 V)
VEE (–5 V ± 0.25 V)
Operating Voltages
Vcc
VLOGIC
VEE
Operating Current
ICC
ILOGIC5
IEE
POWER CONSUMPTION
+4.75
+4.5
–5.25
46
3
46
475
؎1
؎1
؎1
+5.25
+5.5
–4.75
56
6
56
621
+4.75
+4.5
–5.25
46
3
46
475
؎1
؎1
؎1
+5.25
+5.5
–4.75
56
6
56
621
LSB
LSB
LSB
Volts
Volts
Volts
mA
mA
mA
mW
TEMPERATURE RANGE
Specified (J/K)
Specified (S)
0
–55
+70
+125
0
+70 °C
°C
NOTES
1Adjustable to zero with external potentiometers. See Offset/Gain Calibration section for additional information.
2Full-scale range (FSR) is 5 V for the 0 V to 5 V range and 10 V for the 0 V to 10 V and –5 V to +5 V ranges.
325°C to TMIN and 25°C to TMAX.
4Change in gain error as a function of the dc supply voltage.
5Tested under static conditions. See Figure 12 for typical curves of I LOGIC vs. Conversion Rate and Output Loading.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all devices at final electrical test with worst case supply voltages at 0, +25 °C and +70°C. Results from those tests are
used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested.
REV. B
–3–


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AD671–SPECIFICATIONS
DIGITAL SPECIFICATIONS (For all grades TMIN to TMAX, with VCC = +5 V ؎ 5%, VLOGIC = +5 V ؎ 10%, VEE = –5 V
؎ 5%, VREF = +5.000 V, unless otherwise noted)
Parameter
Symbol Min Typ Max
Units
LOGIC INPUT
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = VLOGIC)
Low Level Input Current (VIN = 0 V)
Input Capacitance
VIH
VIL
IIH
IIL
CIN
+2.0
–10
–10
5
V
+0.8 V
+10 µA
+10 µA
pF
LOGIC OUTPUTS
High Level Output Voltage (IOH = 0.5 mA)
VOH
+2.4
V
Low Level Output Voltage (IOL = 1.6 mA)
VOL
+0.4 V
Output Capacitance
COUT
5 pF
Specifications shown in boldface are tested on all devices at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max
specifications are guaranteed, although only those shown in boldface are tested.
Specifications subject to change without notice.
OSWITCHINGBSPECIFICATIONSParameter
SConversion Time
O(AD671-500)
(AD671-750)
LENCODE Pulse Width High
E(AD671-500)
(AD671-750)
TEENCODE Pulse Width Low
(For all grades TMIN to TMAX with VCC = +5 V ؎ 5%, VLOGIC = +5 V ؎ 10%, VEE = –5 V
؎ 5%, VIL = 0.8 V, VIH = 2.0 V, VOL = 0.4 V and VOH = 2.4 V)
Symbol Min Typ Max
Units
tC
tC
tENC
tENC
tENCL
475 500
725 750
ns
ns
20 30 ns
20 50 ns
20 ns
DAV Pulse Width
(AD671-500)
tDAV
75
200 ns
(AD671-750)
tDAV
75
300 ns
ENCODE Falling Edge Delay
tF 0
ns
Start New Conversion Delay
Data and OTR Delay from DAV Falling Edge
Data and OTR Valid before DAV Rising Edge
tR
tDD1
tSS2
0
20 75
20 75
ns
ns
ns
NOTES
1tDD is measured from when the falling edge of DAV crosses 0.8 V to when the output crosses 0.4 V or 2.4 V with a 25 pF load capacitor on each output pin.
2tSS is measured from when the outputs cross 0.4 V or 2.4 V to when the rising edge of DAV crosses 2.4 V with a 25 pF load capacitor on each output pin.
a. Encode Pulse HIGH
b. Encode Pulse LOW
Figure 1. AD671 Timing Diagrams
–4– REV. B


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AD671
ABSOLUTE MAXIMUM RATINGS*
ORDERING GUIDE
With
Temperature Package
Respect
Modell
Linearity Range
Options2
Parameter
to Min Max Units
AD671JD-500 ± 4 LSB
0°C to +70°C
D-24A
VCC
VEE
VLOGIC
ACOM
ACOM –0.5 +6.5
ACOM –6.5 +0.5
DCOM –0.5 +6.5
DCOM –1.0 +1.0
Volts
Volts
Volts
Volts
AD671KD-500
AD671JD-750
AD671KD-750
AD671SD-500
± 2 LSB
± 2 LSB
± 1.5 LSB
± 4 LSB
0°C to +70°C
0°C to +70°C
0°C to +70°C
–55°C to +125°C
D-24A
D-24A
D-24A
D-24A
VCC
VLOGIC –6.5 +6.5
Volts AD671SD-750 ± 2.5 LSB –55°C to +125°C D-24A
ENCODE
REF IN
AIN, BPO/UPO
DCOM –0.5 VLOGIC +0.5 Volts
ACOM –0.5 VCC +0.5 Volts
ACOM –6.5 11.0
Volts
NOTES
1For details on grade and package offerings screened in accordance with
MIL-STD-883, refer to the Analog Devices Military Products Databook or
Junction Temperature
Storage Temperature
Lead Temperature (10 sec)
Power Dissipation
+175
–65 +150
+300
1000
°C
°C
°C
mW
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
Ooperation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
Bmaximum ratings for extended periods may effect device reliability.
current AD671/883 data sheet.
2D = Ceramic DIP.
SOCAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
L WARNING!accumulate on the human body and test equipment and can discharge without detection.
Although the AD671 features proprietary ESD protection circuitry, permanent damage may
Eoccur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
TEprecautions are recommended to avoid performance degradation or loss of functionality.
ESD SENSITIVE DEVICE
REV. B
–5–


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Monolithic 12-Bit 2 MHz A/D Converter

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AD671
Symbol
AD671 PIN DESCRIPTION
Pin Type Name and Function
CONNECTION DIAGRAM
PINOUT
ACOM
AIN
BIT1 (MSB)
BIT2–BIT11
BIT12 (LSB)
22
20
12
11–2
1
P
AI
DO
DO
DO
Analog Ground.
Analog Input Signal.
Most Significant Bit.
Data Bits 2–11.
Least Significant Bit.
BIT12 (LSB) 1
BIT11 2
BIT10 3
BIT9 4
24 VEE
23 VCC
22 ACOM
21 BPO/UPO
BPO/UPO 21 AI Bipolar or Unipolar
BIT8 5
20 AIN
Configuration Pin. Connect to
BIT7 6
AD671 19 REF IN
AIN for 0 V to +5 V Span, to
BIT6 7
TOP VIEW
(Not to Scale)
18 DCOM
ACOM for 0 V to +10 V Span
and to REF IN for –5 V to
+5 V Span.
OBSDAV
15 DO Data Available Output. The
Rising Edge of DAV Indicates
an End of Conversion and Can
Be Used to Latch Current
Data into an External
Register. The Falling Edge of
DAV Can Be Used to Latch
Previous Data into an External
Register.
ODCOM
18 P Digital Ground.
ENCODE 16 DI The AD671 Starts a
LConversion on the Rising
EEdge of the ENCODE Pulse.
TEMSB
13 DO Inverted Most Significant Bit.
Provides Twos Complement
BIT5 8
BIT4 9
BIT3 10
BIT2 11
BIT1 (MSB) 12
17 VLOGIC
16 ENCODE
15 DAV
14 OTR
13 MSB
Output Data Format.
OTR
14 DO Out of Range Is Active HIGH
when the analog input is
beyond the input range of the
converter.
REF IN
19 AI +5 V Reference Input.
VCC
VEE
VLOGIC
23 P +5 V Analog Power.
24 P –5 V Analog Power.
17 P +5 V Digital Power.
TYPE:
AI = Analog Input
DI = Digital Input
DO = Digital Output
P = Power
–6– REV. B


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AD671
DEFINITIONS OF SPECIFICATIONS
GAIN ERROR
INTEGRAL NONLINEARITY (INL)
The last transition (from 1111 1111 1110 to 1111 1111 1111)
Integral nonlinearity refers to the deviation of each individual
should occur for an analog value 1 1/2 LSB below the nominal
code from a line drawn from “zero” through “full scale.” The
full scale (9.9963 volts for 10.000 volts full scale). The gain er-
point used as “zero” occurs 1/2 LSB (1.22 mV for a 10 V span) ror is the deviation of the actual level at the last transition from
before the first code transition (all zeros to only the LSB on).
the ideal level. The gain error can be adjusted to zero as shown
“Full scale” is defined as a level 1 1/2 LSB beyond the last code in Figures 7, 8 and 9.
transition (to all ones). The deviation is measured from the low
side transition of each particular code to the true straight line.
TEMPERATURE COEFFICIENTS
The temperature coefficients for unipolar offset, bipolar zero
DIFFERENTIAL NONLINEARITY (DNL, NO MISSING
and gain error specify the maximum change from the initial
CODES)
(+25°C) value to the value at TMIN or TMAX.
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every
code must have a finite width. Guaranteed no missing codes to
10-bit resolution indicates that all 1024 codes represented by
Bits 1–10 must be present over all operating ranges. Guaranteed
no missing codes to 11- or 12-bit resolution indicates that all
2048 and 4096 codes, respectively, must be present over all op-
Oerating ranges.
BUNIPOLAR OFFSET
The first transition should occur at a level 1/2 LSB above analog
Scommon. Unipolar offset is defined as the deviation of the ac-
Otual from that point. This offset can be adjusted as discussed
later. The unipolar offset temperature coefficient specifies the
Lmaximum change of the transition point over temperature, with
or without external adjustments.
ETBIPOLAR ZERO
EIn the bipolar mode the major carry transition (0111 1111 1111
POWER SUPPLY REJECTION
The only effect of power supply error on the performance of the
device will be a small change in gain. The specifications show
the maximum full-scale change from the initial value with the
supplies at the various limits.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO
S/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components, including har-
monics but excluding dc. The value for S/N+D is expressed in
decibels.
EFFECTIVE NUMBER OF BITS (ENOB)
ENOB is calculated from the expression SNR = 6.02N +
1.8 dB, where N is equal to the effective number of bits.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic com-
to 1000 0000 0000) should occur for an analog value 1/2 LSB
ponents to the rms value of the measured input signal and is ex-
below analog common. The bipolar offset error and temperature pressed as a percentage or in decibels.
coefficient specify the initial deviation and maximum change in
the error over temperature.
PEAK SPURIOUS OR PEAK HARMONIC COMPONENT
The peak spurious or peak harmonic component is the largest
spectral component excluding the input signal and dc. This
value is expressed in decibels relative to the rms value of a full-
scale input signal.
Theory of Operation
The AD671 uses a successive subranging architecture. The ana-
log to digital conversion takes place in four independent steps or
flashes. The analog input signal is subranged to an intermediate
residue voltage for the final 12-bit result by utilizing multiple
flashes with subtraction DACs (see the AD671 functional block
diagram).
The AD671 can be configured to operate with unipolar (0 V to
+5 V, 0 V to +10 V) or bipolar (± 5 V) inputs by connecting
AIN (Pin 20), REFIN (Pin 19) and BPO/UPO (Pin 21) as
shown in Figure 2.
The AD671 conversion cycle begins by simply providing an ac-
tive HIGH pulse on the ENCODE pin (Pin 16). The rising
edge of the ENCODE pulse starts the conversion. The falling
edge of the ENCODE pulse is specified to operate within a win-
dow of time: less than 30 ns after the rising edge of ENCODE
(AD671-500) and less than 50 ns after the falling edge of
ENCODE (AD671–750) or after the falling edge of DAV. The
time window prevents digitally coupled noise from being intro-
duced during the final stages of conversion. An internal timing
generator circuit accurately controls all internal timing.
ACOM 22
BPO/UPO 21
AIN 20
AIN
REF IN 19 +5V REF
0 TO +5V
BPO/UPO 21
AIN 20
AIN
REF IN 19
+5V REF
0 TO +10V
BPO/UPO 21
AIN 20
AIN
REF IN 19
+5V REF
–5V TO +5V
Figure 2. Input Range Connections
REV. B
–7–


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AD671
Upon receipt of an ENCODE command, the first 3-bit flash
INPUT BUFFER AMPLIFIER
converts the analog input voltage. The 3-bit result is passed to a The closed-loop output impedance of an op amp is equal to the
correction logic register and a segmented current output DAC. open loop output impedance (usually a few hundred ohms) di-
The DAC output is connected through a resistor (within the
vided by the loop gain at the frequency of interest. It is often
Range/Span Select Block) to AIN. A residue voltage is created
assumed that loop gain of a follower-connected op amp is suffi-
by subtracting the DAC output from AIN, which is less than
ciently high to reduce the closed-loop output impedance to a
one eighth of the full-scale analog input. The second flash has
negligibly small value, particularly if the input signal is low
an input range that is configured with one bit of overlap with the frequency. At higher frequencies the open-loop gain is lower,
previous DAC. The overlap allows for errors during the flash
increasing the output impedance which decreases the instanta-
conversion. The first residue voltage is connected to the second neous analog input voltage and produces an error.
3-bit flash and to the noninverting input of a high speed, differ- The recommended wideband, fast settling input amplifiers for
ential, gain-of-four amplifier. The second flash result is passed
use with the AD671 are the AD841, AD843, AD845 or the
to the correction logic register and to the second segmented cur- AD847. The AD841 is unity gain stable and recommended as a
rent output DAC. The output of the second DAC is connected
to the inverting input of the differential amplifier. The differen-
tial amplifier output is connected to a two step backend 8-bit
flash. This 8-bit flash consists of coarse and fine flash convert-
ers. The result of the coarse 4-bit flash converter, also config-
ured to overlap one bit of DAC 2, is connected to the correction
Ologic register and selects one of 16 resistors from which the fine
4-bit flash will establish its span voltage. The fine 4-bit flash is
Bconnected directly to the output latches.
The AD671 will flag an out-of-range condition when the input
Svoltage exceeds the analog input range. OTR (Pin 14) is active
OHIGH when an out of range high or low condition exists. Bits
1–12 are HIGH when the analog input voltage is greater than
Lthe selected input range and LOW when the analog input is less
Ethan the selected input range.
TEAPPLYING THE AD671
follower connected op amp. The AD843 and AD845 FET in-
puts make them ideal for high speed sample-and-hold amplifiers
and the AD847 can be used as a low power, high speed buffer.
Figure 4 shows the AD841 driving the AD671. As shown in the
figure the analog input voltage should be produced with respect
to the ACOM pin.
4 11
AD841 10
+ 56
±5V
23
VCC
20 AIN
24 17
VEE VLOGIC
BIT1 1
BIT12 12
22 ACOM
18 DCOM
ENCODE 16
DAV 15
DRIVING THE AD671 ANALOG INPUT
+5V REF
19 REF IN
OTR 14
The AD671 uses a very high speed current output DAC to sub-
tract a known voltage from the analog input. This results in very
21 BPO/UPO
MSB 13
fast steps of current at the analog input. It is important to recog-
AD671
nize that the signal source driving the analog input of the
AD671 must be capable of maintaining the input voltage under
Figure 4. Input Buffer Amplifier
dynamically-changing load conditions. When the AD671 starts
its conversion cycle, the subtraction DAC will sink up to 5 mA
(see Figure 3) from the source driving the analog input. The
source must respond to this current step by settling the input
voltage back to a fraction of an LSB before the AD671 makes its
final 12-bit decision.
REFERENCE INPUT
The AD671 uses a standard +5 volt reference. The initial accu-
racy and temperature stability of the reference can be selected to
meet specific system requirements. Like the analog input, fast
switching input-dependent currents are modulated at the refer-
ence input pin (REF IN–Pin 19). However, unlike the analog
input the reference input is held at a constant +5 volts with the
+ IIN
R
use of capacitor. The recommended reference is the AD586, a
+5 V precision reference with an output buffer amplifier. Fig-
ure 5 shows the AD671 configured in the ± 5 V input range.
A/D
IA/D
AD671
DAC
IDAC
The 6.8 µF capacitor maintains a constant +5 volts under the
dynamically changing load conditions. An optional 1 µF noise
reduction capacitor can be connected to the AD586, further re-
ducing broadband output noise. To minimize ground voltage
Figure 3. Driving the Analog Input
drops the AD586’s ground pin should be tied as close as pos-
Unlike successive approximation A/Ds, where the input voltage
must settle to a fraction of a 12-bit LSB before each successive
sible to the AD671’s ACOM pin. See Figures 20, 21 and 22 for
PCB layout recommendations.
bit decision is made, the AD671 requires the analog input volt-
age settle to within 12 bits before the third flash conversion,
approximately 200 ns. This “free” 200 ns is useful in applica-
tions requiring a sample-and-hold amplifier (SHA), overlapping
the SHA’s hold mode settling time within the 200 ns window
will increase total system throughput. See the “Discrete Sample-
and-Hold” section for a high speed SHA application.
–8– REV. B


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+15V ±5V
2
AD586 +VIN
8 U4
VOUT
NOISE
6
1µF REDUCTION 6.8µF
C14 GND C15
4
23 24 17
VCC VEE VLOGIC
20 AIN
BIT1 1
U3 BIT12 12
22 ACOM ENCODE 16
18 DCOM
DAV 15
19 REF IN
OTR 14
21 BPO/UPO MSB 13
AD671
Table I. Grounding and Decoupling Guidelines
Power Supply
Decoupling
Comment
Capacitor Values
0.1 µF (Ceramic) and 10 µF (Tantalum).
(Surface Mount Chip Capacitors Recom-
mended to Reduce Lead Inductance).
Capacitor Locations Directly at Positive and Negative
Supply Pins to Respective Ground Plane.
Grounding
Analog Ground
Ground Plane or Wide Ground Return
Figure 5. AD586 as Reference Input for AD671
GROUNDING AND DECOUPLING RULES
Proper grounding and decoupling should be a primary design
objective in any high speed, high resolution system. The AD671
Oseparates analog and digital grounds to optimize the manage-
ment of analog and digital ground currents in a system. The
BAD671 is designed to minimize the current flowing from
ACOM (Pin 22) by directing the majority of the current from
SVCC (+5 V–Pin 23) to VEE (–5 V–Pin 24). Minimizing analog
Oground currents hence reduces the potential for large ground
voltage drops. This can be especially true in systems that do not
Lutilize ground planes or wide ground runs. ACOM is also con-
Efigured to be code independent, therefore reducing input depen-
dent analog ground voltage drops and errors. The input current
TEsupplied by the external reference (REFIN–Pin 19) and the ma-
Digital Ground
Analog and Digital
Ground
Connected to the Analog Power Supply.
Ground Plane or Wide Ground Return
Connected to the Digital Power Supply.
Connected Together Once at the AD671.
UNIPOLAR (0 V TO +10 V) CALIBRATION
The AD671 is factory trimmed to minimize offset, gain and lin-
earity errors. In some applications the offset and gain errors of
the AD671 need to be externally adjusted to zero. This is ac-
complished by trimming the voltage at BPO/UPO (Pin 21) and
REFIN (Pin 19). In those applications the AD588, a high preci-
sion pin programmable voltage reference, is an ideal choice. The
AD588 includes a reference cell and three additional amplifiers
which can be configured to provide offset and gain trims for the
jority of the full-scale input signal (AIN–Pin 20) are also di-
AD671. The circuit in Figure 7 is recommended for calibrating
rected to VÉE. Also critical in any high speed digital design are
offset and gain errors of the AD671 when configured in the 0 V
the use of proper digital grounding techniques to avoid potential to +10 V input range.
CMOS “ground bounce.” Figure 6 is provided to assist in the
proper layout, grounding and decoupling techniques.
+5V –5V +5V
Table I is a list of grounding and decoupling guidelines that
10µF 10µF 10µF
should be reviewed before laying out a printed circuit board.
0.1µF 0.1µF 0.1µF
+5V –5V +5V
10µF 10µF 10µF
+15V
39k
23
VCC
0 TO +10V
20 AIN
24
VEE
17
VLOGIC
BIT1 12
R1 BIT12 1
100
22 ACOM ENCODE 16
0.1µF 0.1µF 0.1µF
23 24 17
VCC VEE
VLOGIC
+
20 AIN
BIT1 12
VIN ±5V
AGP*
DGP*
BIT12 1
22 ACOM
18 DCOM
ENCODE 16
DAV 15
150pF
1µF 7 6 4 3
50
1
10µF
14
AD588
1µF 10k
15
150 10µF
2 +15
16 –15
5 9 10 8 12 11 13
100k
R2
5k 50
18 DCOM
DAV 15
19 REF IN
0.1µF
21 BPO/UPO
OTR 14
MSB 13
0.1µF
AD671
+5V REF
19 REF IN
OTR 14
21 BPO/UPO MSB 13
AD671
*GROUND PLANE RECOMMENDED
Figure 6. AD671 Grounding and Decoupling
Figure 7. Unipolar (0 V to +10 V) Calibration
The AD671 is intended to have a nominal 1/2 LSB offset so
that the exact analog input for a given code will be in the middle
of that code (halfway between the transitions to the codes above
it and below it). Thus, the first transition ( from 0000 0000 0000
to 0000 0000 0001) will occur for an input level of +1/2 LSB
(1.22 mV for 10 V range). If the offset trim resistor R2 is used,
REV. B
–9–


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it should be trimmed as above, although a different offset can be
set for a particular system requirement. This circuit will give ap-
proximately ± 50 mV of offset trim range.
The gain trim is done by applying a signal 1 1/2 LSBs below the
nominal full scale (9.9963 for a 10 V range). Trim R1 to give
the last transition (1111 1111 1110 to 11111111 1111).
Bipolar calibration is similar to unipolar calibration. First, a sig-
nal 1/2 LSB above negative full scale (–4.9988 V) is applied and
R1 is trimmed to give the first transition (0000 0000 0000 to
0000 0000 0001). Then a signal 1 1/2 LSB below positive full
scale (+4.9963) is applied, and R2 is trimmed to give the last
transition (1111 1111 1110 to 1111 1111 1111).
UNIPOLAR (0 V TO +5 V) CALIBRATION
OUTPUT LATCHES
The connections for the 0 V to +5 V input range calibration is
Figure 10 shows the AD671 connected to the 74HC574 Octal
shown in Figure 8. The AD586, a +5 V precision voltage refer- D-type edge triggered latches with 3-state outputs. The latch
ence, is an excellent choice for this mode of operation because
can drive highly capacitive loads (i.e., bus lines, I/O ports) while
of its performance, stability and optional fine trim. The AD845 maintaining the data signal integrity. The maximum set-up and
(16 MHz, low power, low cost op amp) is used to maintain the
hold times of the 574 type latch must be less than 20 ns (tDD
+5 volts under the dynamically changing load conditions of the
reference input.
+15V
0.1µF
27
O 0 TO+5V
3
AD845
8
4 1 1k
6
B+15V
S2
+VIN
–15V
0.1µF
390
+15V
VOUT 6
27
AD845
34
0.1µF
6
O8 NOISE TRIM 5
REDUCTION
10k
0.1µF
–15V
23
VCC
20 AIN
24
VEE
21 BPO/UPO
+15V
17
VLOGIC
BIT1 12
BIT12 1
22 ACOM ENCODE 16
18 DCOM
DAV 15
19 REFIN
OTR 14
MSB 13
AD671
L1µF AD586
EGND
4
TEFigure 8. Unipolar (0 V to +5 V) Calibration
and tSS minimum). To satisfy the requirements of the 574 type
latch the recommended logic families are HC, S, AS, ALS, F or
BCT. New data from the AD671 is latched on the rising edge of
the DAV (Pin 24) output pulse. Previous data can be latched by
inverting the DAV output with a 7404 type inverter. See Fig-
ures 20, 21 and 22 for PCB layout recommendations.
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
BIT8
DAV
BIT9
BIT10
BIT11
BIT12
74HC574
1D 1Q
2D 2Q
3D 3Q
4D 4Q
5D U6 5Q
6D 6Q
7D 7Q
8D 8Q
CLK OC
74HC574
1D 1Q
2D 2Q
3D 3Q
4D 4Q
5D U5 5Q
DATA BUS
The AD671 offset error must be trimmed within the analog in-
6D 6Q
7D 7Q
put path, either directly in front of the AD671 or within the sig-
nal conditioning chain, eliminating offset errors induced by the
AD671
8D
CLK
8Q
OC
3-STATE
CONTROL
signal conditioning circuitry. Figure 8 shows an example of how
the offset error can be trimmed in front of the AD671. The
Figure 10. AD671 to Output Latches
AD586 is configured in the optional fine trim mode to provide
+6%/–2% (+240 LSBs/–80 LSBs) of gain trim. The procedure
for trimming the offset and gain errors is similar to that used for
the unipolar 10 V range with the analog input values set to one-
half the 10 V range values.
OUT OF RANGE
An Out of Range condition exists when the analog input voltage
is beyond the input range (0 V to +5 V, 0 V to +10 V, ± 5 V) of
the converter. OTR (Pin 14) is set low when the analog input
voltage is within the analog input range. OTR is set HIGH and
BIPOLAR (؎5 V) CALIBRATION
The connections for the bipolar input range is shown in Figure
9. The AD588 is configured to provide dual +5 V outputs. Pro-
viding a +5 V reference voltage for the AD671 gain trim and the
+5 V BPO/UPO input for the bipolar offset trim.
will remain HIGH when the analog input voltage exceeds the
input range by typically 1/2 LSB (OTR transition is tested to
± 6 LSBs of accuracy) from the center of the ± full-scale output
codes. OTR will remain HIGH until the analog input is within
the input range and another conversion is completed. By logical
ANDing OTR with the MSB and its complement overrange
+15V
6.2k
39k
R1
100
± 5V
23
VCC
20 AIN
24
VEE
17
VLOGIC
BIT1 12
BIT12 1
22 ACOM ENCODE 16
high or underrange low conditions can be detected. Table II is a
truth table for the over/under range circuit in Figure 11. Sys-
tems requiring programmable gain conditioning prior to the
AD671 can immediately detect an out of range condition, thus
eliminating gain selection iterations.
150pF
1µF 7 6 4 3
50
1
14 10µF
AD588
150pF
R2
100
15
50 10µF
2 +15
16 –15
5 9 10 8 12 11 13
18 DCOM
DAV 15
19 REF IN
0.1µF
21 BPO/UPO
OTR 14
MSB 13
AD671
0.1µF
Table II. Out of Range Truth Table
OTR
MSB
Analog Input Is
0 0 In Range
0 1 In Range
1 0 Underrange
1 1 Overrange
Figure 9. Bipolar (±5 V) Calibration
–10–
REV. B


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MSB
OTR
OVER = "1"
MSB
UNDER = "1"
Figure 11. Overrange or Underrange Logic
OUTPUT DATA FORMAT
The AD671 provides both MSB and MSB outputs, delivering
data in positive true straight binary for unipolar input ranges
and positive true offset binary or twos complement for bipolar
input ranges. Straight binary coding is used for systems that ac-
cept positive-only signals. If straight binary coding is used with
bipolar input signals a 0 V input would result in a binary output
of 2048. The application software would have to subtract 2048
to determine the true input voltage. Most processors typically
perform math on signed integers and assume data is in that for-
mat. Twos complement format minimizes software overhead
which is especially important in high speed data transfers, such
as a DMA operation. The CPU is not bogged down performing
data conversion steps, hence increasing the total system
throughput.
Input
Range
0 to +5 V
OBS0 to +10 V
OLETE–5Vto+5V
Table III. Output Data Format
Coding
Straight Binary
Straight Binary
Offset Binary
Analog
Input1
–0.00061 V
0V
+5 V
>+5.00061 V
–0.00122 V
0V
+10 V
+10.00122 V
–5.00122 V
–5 V
0V
Digital
Output
0000 0000 0000
0000 0000 0000
1111 1111 1111
1111 1111 1111
0000 0000 0000
0000 0000 0000
1111 1111 1111
1111 1111 1111
0000 0000 0000
0000 0000 0000
1000 0000 0000
OTR2
1
0
0
1
1
0
0
1
1
0
0
+4.99756 V
1111 1111 1111
0
+4.99878 V 1111 1111 1111
1
–5 V to +5 V 2s Complement
(Using MSB)
–5.00122 V
–5 V
0V
+4.99756 V
+4.99878 V
1000 0000 0000
1000 0000 0000
0000 0000 0000
0111 1111 1111
0111 1111 1111
1
0
0
0
1
NOTES
1Voltages listed are with offset and gain errors adjusted to zero.
2Typical performance.
ILOGIC vs. CONVERSION RATE
Figure 12 shows the typical logic supply current vs. conversion
rate for various capacitive loads on the digital outputs.
REV. B
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
1k
CL = 50pF
CL = 30pF
CL = 0pF
10k 100k
1M
CONVERSION RATE – Hz
10M
Figure 12. ILOGIC vs. Conversion Rate for Various
Capacitive Loads on the Digital Outputs
–11–


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HIGH PERFORMANCE SAMPLE-AND-HOLD
CROSS COUPLED LATCH
AMPLIFIER (SHA)
In order to take full advantage of the AD671’s high speed capa-
bilities, a sample-and-hold amplifier (SHA) with fast acquisition
capabilities and rigid accuracy requirements is essential. One
possibility is a hybrid SHA such as the HTC-0300A, but often a
As noted in the Theory of Operation, the ENCODE pulse is
specified to operate within a window of time. The circuit in Fig-
ure 14 can be used to generate a valid ENCODE pulse if a clock
pulse width of greater than 30 ns is available.
cost effective alternative like the one shown in Figure 13 may be
a better solution. This discrete SHA requires very few compo-
nents and is able to acquire signals to 0.01% accuracy in less
than 350 nanoseconds. Combined with the AD671, signals with
bandwidths up to 500 kHz can be converted with 12-bit accuracy.
1/4
tw
7402
AD671
1/4
7402
ENCODE
R9
1/4
7402
DAV
R7
–15V
1k
C28
VIN R6
OBSO(5Vp–p) 2k
1k
+15V
C24
4
0.1µF
11
U8
AD841 10
5 6 C25
R8
250
0.1µF
–15V
R11
250
S/H
S/H
R10
10k D1
1N4148
2
SD5001
4 IN1
OUT1 1
5 IN2
OUT2 8
U10
13 IN3
OUT3 16
12 IN4
OUT4 9
G1 G2 G3 G4
3 6 14 11
20pF
+15V
C26
2 7 0.1µF
U9
AD845 6
3 4 C27
C29 –15V 0.1µF
20pF
C34
5pF
R13
1k
VR2 100k
R14
226
PEDESTAL ADJ
LFigure 13. Discrete High Speed Sample-and-Hold Amplifier
ETCIRCUIT DESCRIPTION
EThe discrete SHA shown in Figure 13 is a closed-loop, nonin-
Figure 14. Cross Coupled Latch
TIMING DESCRIPTION
Figure 15 shows the timing requirements for the discrete SHA.
The complementary S/H inputs are HCMOS-compatible al-
though larger gate voltages will improve performance by lower-
ing the on resistances of the DMOS switches. It should be noted
that a conversion is started before the SHA has settled to 0.01%
accuracy. The discrete SHA takes advantage of the fact that the
AD671 does not require a 12-bit accurate input until it is 150 ns
into its conversion cycle. See Figures 21, 22 and 23 for PCB
layout recommendations.
ENCODE
t SAMPLE = 1µs
verting architecture which accepts 5 V p-p inputs. The overall
gain of the SHA is +2 in order to accommodate the 10 V input
t CONVERSION = 500ns
span of the AD671. The AD841, with a 0.01% settling time of
110 ns, is the suggested input buffer to the SHA. The circuit
also employs a SD5001 which contains four ultrahigh speed
DMOS switches (Q1–Q4). The high CMRR, low input offset
DAV
t ACQUIRE
350ns
t SETTLE
350ns
current, and fast settling time of the AD845 op amp are all criti-
cal features necessary for optimal performance of the discrete
S/H
SHA.
Figure 15. AD671 to Discrete SHA Timing Diagram
In sample mode, Q1 and Q3 of the SD5001 are closed (Q2 and
Q4 are open). C28 is charged to the input voltage level at a rate
primarily determined by the time constant, R9 • C28. Simulta-
neously, C29 is connected to ground through a 250 ohm resis-
tor. If C28 is equal to C29, charge injection from Q1 will be
approximately equal to charge injection from Q3 based on the
symmetry of the circuit and the inherent matching of the switch
capacitances. The resultant pedestal errors appear as a common-
DYNAMIC PERFORMANCE
In most sampling applications the dynamic performance of the
system is limited by the performance of the SHA. The SHA’s
dynamic performance can be selected to meet the system sam-
pling requirements. Figures 16 and 17 are typical FFT plots
using the discrete SHA in Figure 13.
mode signal to the AD845. VR2, R13, R14, and C34 may be in-
cluded if further reduction of pedestal error is required.
In hold mode, Q2 and Q4 are closed (Q1 and Q3 are open) to
reduce feedthrough. The input signal is attenuated –78 dB
relative to the input signal at frequencies up to 500 kHz. The
AD845 buffers the voltage on C28 and also provides the wide-
band, low-impedance output necessary to drive the input of the
AD671.
Droop, which occurs as a result of leakage currents, will appear
on C28 and will similarly appear on C29. Like pedestal errors,
droop appears as a common-mode signal to the AD845 and is
greatly reduced by the differential nature of the circuit. Voltage
droop is typically 5 µV/µs.
Figure 16. Typical FFT Plot of AD671 and Discrete SHA
FIN = 100 kHz
–12–
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DYNAMIC CHARACTERISTICS
(@ +25°C, tested using the discrete SHA in Figure 15 with VCC = +5 V,
VLOGIC = +5 V, VEE = –5 V, fSAMPLE = 1 MSPS)1
Model
AD671JD-500
Typ Units
Effective Number of Bits (ENOB)
FIN = 100 kHz
FIN = 490 kHz
11.3 Bits
11.2 Bits
Signal-to-Noise and Distortion (S/N+D) Ratio
Figure 17. Typical FFT Plot of AD671 and Discrete SHA
FIN = 100 kHz
FIN = 490 kHz
70 dB
68 dB
FIN = 500 kHz
MULTICHANNNEL DATA ACQUISITION SYSTEM
The AD684, a quad high speed sample-and-hold amplifier is
ideally suited for multichannel data acquisition applications.
Figure 18 shows a typical data acquisition circuit using the
OAD684 (SHA), ADG201HS (Multiplexer), AD588 (Reference)
Band the AD671. The AD684 is configured to simultaneously
sample four analog inputs. Each held analog input voltage can
Sbe selected by the multiplexer and buffered by the AD841. The
OLETEAD671 is connected in the bipolar input range (±5 V).
Total Harmonic Distortion (THD)
FIN = 100 kHz
FIN = 490 kHz
Peak Spurious (dc to 490 kHz)
–80 dB
–75 dB
–79 dB
Peak Harmonic Component (dc to 490 kHz) –76 dB
NOTE
1fIN amplitude = –0.2 dB @ 100 kHz and –0.9 dB @ 490 kHz, bipolar mode
unless otherwise indicated. See Definition of Specifications for additional
information.
Figure 18. Data Acquisition System Using the AD684 and the AD671
REV. B
–13–


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AD671 TO ADSP-2100A INTERFACE
Figure 19 demonstrates the AD671 to ADSP-2100A interface.
The 2100A with a clock frequency of 12.5 MHz can execute an
instruction in one 80 ns cycle. The AD671 is configured to per-
form continuous time sampling. The DAV output of the AD671
is asserted at the end of each conversion. DAV can be used to
latch the conversion result into the two 574 octal D-latches. The
falling edge of the sampling clock is used to generate an inter-
rupt (IRQ3) for the processor. Upon interrupt, the ADSP-
2100A starts a data memory read by providing an address on
the DMA bus. The decoded address generates OE for the
latches and the processor reads their output over the DMA bus.
The conversion result is read within a single processor cycle.
DMRD
DMA0:13 ADDRESS BUS
ADSP-2100A
DMA0:15
DMACK
DECODE
16
DATA BUS
+ 5V
8
8
IRQ3
SAMPLING
CLOCK
OE
574
Q0:7
D0:7
8
OE
574
D0:3
Q0:7
D0:7
4
4
DAV
AD671
BIT1:12
ENCODE
AD671 TO ADSP-2101/ADSP-2102 INTERFACE
Figure 20 is identical to the 2100A interface except the sam-
pling clock is used to generate an interrupt (IRQ2) for the pro-
cessor. Upon interrupt the ADSP-2101A starts a data memory
read by providing an address on the Address (A) bus. The de-
Ocode address generates OE for the D-latches and the processor
reads their output over the Data (D) bus. Reading the conver-
BSOLETEsion result is thus completed within a single processor cycle.
Figure 19. AD671 to ADSP-2100A Interface
RD
A0:13 ADDRESS BUS
ADSP-2101
D0:15
DECODE
16
DATA BUS
8
8
IRQ2
SAMPLING
CLOCK
OE
574
Q0:7
D0:7
8
OE
574
D0:3
Q0:7
D0:7
4
4
DAV
AD671
BIT1:12
ENCODE
Figure 20. AD671 to ADSP-2101/ADSP-2102 Interface
Figure 21. PCB Silkscreen and Component Placement
Diagram for Figures 5, 10 and 13
–14–
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OBSOLETEFigure 22. PCB Solder Side Layout for Figures 5, 10 and 13
Figure 23. PCB Component Side Layout for Figures 5, 10 and 13
REV. B
–15–


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OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Pin Plastic DIP (Suffix N)
OBSOLETE24-Pin Ceramic DIP (Suffix D)
PIN 1
1
1.200 Ϯ 0.012
(30.48 Ϯ 0.31)
0.295 Ϯ 0.01
(7.49 Ϯ 0.26)
0.300 Ϯ 0.010
(7.49 Ϯ 0.25)
SEATING
PLANE
0.175
(4.45)
0.085 Ϯ 0.009
(2.16 Ϯ 0.23)
0.018 Ϯ 0.002 0.100 Ϯ 0.005
(0.46 Ϯ 0.05) (2.54 Ϯ 0.13)
TYP
0.05 (1.27)
TYP
1.100 Ϯ 0.005
(27.94 Ϯ 0.13)
TOLL NON ACCUM
NOTES
1. LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH.
2. CERAMIC DIP LEADS WILL BE EITHER GOLD OR TIN PLATED
IN ACCORDANCE WITH MIL-M-385 TO REQUIREMENTS.
+ 0.002
0.010
–0.001
+ 0.05
( )0.025 –0.03
–16–
REV. B



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