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AD6645 Datasheet
80 MSPS/105 MSPS A/D Converter

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14-Bit, 80 MSPS/105 MSPS
A/D Converter
AD6645
FEATURES
SNR = 75 dB, fIN 15 MHz, up to 105 MSPS
SNR = 72 dB, fIN 200 MHz, up to 105 MSPS
SFDR = 89 dBc, fIN 70 MHz, up to 105 MSPS
100 dBFS multitone SFDR
IF sampling to 200 MHz
Sampling jitter: 0.1 ps
1.5 W power dissipation
Differential analog inputs
Pin compatible to AD6644
Twos complement digital output format
3.3 V CMOS compatible
Data-ready for output latching
APPLICATIONS
Multichannel, multimode receivers
Base station infrastructures
AMPS, IS-136, CDMA, GSM, W-CDMA
Single channel digital receivers
Antenna array processing
Communications instrumentation
Radars, infrared imaging
Instrumentation
GENERAL DESCRIPTION
The AD6645 is a high speed, high performance, monolithic 14-bit
analog-to-digital converter (ADC). All necessary functions,
including track-and-hold (T/H) and reference, are included on the
chip to provide a complete conversion solution. The AD6645
provides CMOS-compatible digital outputs. It is the fourth
generation in a wideband ADC family, preceded by the AD9042
(12-bit, 41 MSPS), the AD6640 (12-bit, 65 MSPS, IF sampling),
and the AD6644 (14-bit, 40 MSPS/65 MSPS).
Designed for multichannel, multimode receivers, the AD6645 is
part of the Analog Devices, Inc., SoftCell® transceiver chipset.
The AD6645 maintains 100 dB multitone, spurious-free dynamic
range (SFDR) through the second Nyquist band. This breakthrough
performance eases the burden placed on multimode digital
receivers (software radios) that are typically limited by the ADC.
Noise performance is exceptional; typical signal-to-noise ratio
(SNR) is 74.5 dB through the first Nyquist band.
The AD6645 is built on the Analog Devices extra fast
complementary bipolar (XFCB) process and uses an innovative,
multipass circuit architecture. Units are available in thermally
enhanced 52-lead PowerQuad 4 (LQFP_PQ4) and 52-lead
exposed pad (TQFP_EP) packages specified from −40°C to
+85°C at 80 MSPS and −10°C to +85°C at 105 MSPS.
PRODUCT HIGHLIGHTS
1. IF Sampling. The AD6645 maintains outstanding ac
performance up to input frequencies of 200 MHz, suitable
for multicarrier 3G wideband cellular IF sampling receivers.
2. Pin Compatibility. The ADC has the same footprint and
pin layout as the AD6644 14-bit, 40 MSPS/65 MSPS ADC.
3. SFDR Performance and Oversampling. Multitone SFDR
performance of 100 dBFS can reduce the requirements of
high end RF components and allows the use of receive
signal processors, such as the AD6620, AD6624/AD6624A,
or AD6636.
AVCC
DVCC
FUNCTIONAL BLOCK DIAGRAM
AIN
A1 TH1
AIN
TH2
AD6645
A2 TH3
TH4
TH5 ADC3
VREF
2.4V
ENCODE
ENCODE
INTERNAL
TIMING
ADC1
DAC1
5
ADC2
DAC2
5
DIGITAL ERROR CORRECTION LOGIC
6
GND
DMID OVR DRY D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
Figure 1.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002–2008 Analog Devices, Inc. All rights reserved.


AD6645 Datasheet
80 MSPS/105 MSPS A/D Converter

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AD6645* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
View a parametric search of comparable parts
Evaluation Kits
• AD6645 Evaluation Board
Documentation
Application Notes
• AN-1142: Techniques for High Speed ADC PCB Layout
• AN-282: Fundamentals of Sampled Data Systems
• AN-345: Grounding for Low-and-High-Frequency Circuits
• AN-501: Aperture Uncertainty and ADC System
Performance
• AN-586: LVDS Outputs for High Speed A/D Converters
• AN-715: A First Approach to IBIS Models: What They Are
and How They Are Generated
• AN-737: How ADIsimADC Models an ADC
• AN-741: Little Known Characteristics of Phase Noise
• AN-756: Sampled Systems and the Effects of Clock Phase
Noise and Jitter
• AN-807: Multicarrier WCDMA Feasibility
• AN-808: Multicarrier CDMA2000 Feasibility
• AN-835: Understanding High Speed ADC Testing and
Evaluation
• AN-905: Visual Analog Converter Evaluation Tool Version
1.0 User Manual
• AN-935: Designing an ADC Transformer-Coupled Front
End
Data Sheet
• AD6645: 14-Bit, 80 MSPS/105 MSPS A/D Converter Data
Sheet
Software and Systems Requirements
• Military Part Cross-Reference Guide
• Military Products by Function
• Military Products by GENERIC Part Number
Tools and Simulations
• Visual Analog
• AD6645 IBIS Models
Reference Designs
• CN0109
Reference Materials
Customer Case Studies
• Ball Aerospace Case Study
Technical Articles
• Buffer Adapts Single-ended Signals for Differential Inputs
• Cascaded Transformers Achieve Better Frequency
Performance in High-Speed ADC
• Converters for 3G are Optimized for Cost, Size and Power
• Correlating High-Speed ADC Performance to Multicarrier
3G Requirements
• DNL and Some of its Effects on Converter Performance
• MS-2210: Designing Power Supplies for High Speed ADC
• MS-2735: Maximizing the Dynamic Range of Software-
Defined Radio
Design Resources
• AD6645 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
View all AD6645 EngineerZone Discussions
Sample and Buy
Visit the product page to see pricing options
Technical Support
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number
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
the content on this page does not constitute a change to the revision number of the product data sheet. This content may be
frequently modified.


AD6645 Datasheet
80 MSPS/105 MSPS A/D Converter

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AD6645
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
General Description ......................................................................... 1 
Product Highlights ........................................................................... 1 
Functional Block Diagram .............................................................. 1 
Revision History ............................................................................... 2 
Specifications..................................................................................... 3 
DC Specifications ......................................................................... 3 
Digital Specifications ................................................................... 4 
AC Specifications.......................................................................... 4 
Switching Specifications .............................................................. 5 
Absolute Maximum Ratings............................................................ 7 
Thermal Resistance ...................................................................... 7 
REVISION HISTORY
10/08—Rev. C to Rev. D
Added TQFP_EP Package ............................................ Throughout
Renamed Thermal Characteristics Section Thermal Resistance
Section................................................................................................ 7
Added Table 6; Renumbered Sequentially .................................... 7
Moved Equivalent Circuits Section.............................................. 14
Moved Terminology Section......................................................... 15
Changes to Table 9.......................................................................... 20
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 24
12/06—Rev. B to Rev. C
Updated Format..................................................................Universal
Changes to Specifications ................................................................ 3
Changes to Jitter Considerations Section .................................... 19
Changes to Table 8, Bill of Materials............................................ 20
Changes to Figure 43, Evaluation Board Schematic .................. 21
Changes to Figure 44 and Figure 46............................................. 22
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide .......................................................... 23
Explanation of Test Levels............................................................7 
ESD Caution...................................................................................7 
Pin Configuration and Function Descriptions..............................8 
Typical Performance Characteristics ..............................................9 
Equivalent Circuits......................................................................... 14 
Terminology .................................................................................... 15 
Theory of Operation ...................................................................... 17 
Applying the AD6645 ................................................................ 17 
Layout Information ........................................................................ 19 
Jitter Considerations .................................................................. 19 
Outline Dimensions ....................................................................... 24 
Ordering Guide .......................................................................... 24 
7/03—Rev. A to Rev. B.
Changes to Title ................................................................................1
Changes to Features ..........................................................................1
Changes to Product Description .....................................................1
Changes to Specifications.................................................................3
Changes to Absolute Maximum Ratings........................................7
Changes to Ordering Guide .......................................................... 24
Updated Outline Dimensions....................................................... 20
6/02—Rev. 0 to Rev. A.
Change to DC Specifications ...........................................................3
Rev. D | Page 2 of 24


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80 MSPS/105 MSPS A/D Converter

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AD6645
SPECIFICATIONS
DC SPECIFICATIONS
AVCC = 5 V, DVCC = 3.3 V; TMIN and TMAX at rated speed grade, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
POWER SUPPLY REJECTION RATIO
(PSRR)
REFERENCE OUT (VREF)1
ANALOG INPUTS (AIN, AIN)
Differential Input Voltage Range
Differential Input Resistance
Differential Input Capacitance
POWER SUPPLY
Supply Voltages
AVCC
DVCC
Supply Current
IAVCC (AVCC = 5.0 V)
IDVCC (DVCC = 3.3 V)
Rise Time2
AVCC
POWER CONSUMPTION
Temp
Full
Full
Full
Full
Full
Full
Full
25°C
Full
Full
Full
25°C
Full
Full
Full
Full
Full
Full
Test Level
II
II
II
II
V
V
V
V
V
V
V
II
II
II
II
IV
II
AD6645ASQ-80/AD6645ASV-80
Min Typ
Max
14
Guaranteed
−10 +1.2
+10
−10 0
+10
−1.0 ±0.25
+1.5
±0.5
1.5
48
±1.0
2.4
2.2
1
1.5
4.75 5.0
3.0 3.3
275
32
1.5
5.25
3.6
320
45
250
1.75
AD6645ASQ-105/AD6645ASV-105
Min Typ Max
14
Guaranteed
−10 +1.2 +10
−10 0
+10
−1.0 ±0.5 +1.5
±1.5
1.5
48
±1.0
2.4
2.2
1
1.5
4.75 5.0
3.0 3.3
275
32
5.0
1.5
5.25
3.6
320
45
250
1.75
Unit
Bits
mV
% FS
LSB
LSB
ppm/°C
ppm/°C
mV/V
V
V p-p
pF
V
V
mA
mA
ms
W
1 VREF is provided for setting the common-mode offset of a differential amplifier, such as the AD8138, when a dc-coupled analog input is required. VREF should be
buffered if used to drive additional circuit functions.
2 Specified for dc supplies with linear rise time characteristics.
Rev. D | Page 3 of 24


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80 MSPS/105 MSPS A/D Converter

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AD6645
DIGITAL SPECIFICATIONS
AVCC = 5 V, DVCC = 3.3 V; TMIN and TMAX at rated speed grade, unless otherwise noted.
Table 2.
Parameter
ENCODE INPUTS (ENCODE, ENCODE)
Differential Input Voltage1
Differential Input Resistance
Differential Input Capacitance
LOGIC OUTPUTS (D13 to D0, DRY, OVR)
Logic Compatibility
Logic 1 Voltage (DVCC = 3.3 V)2
Logic 0 Voltage (DVCC = 3.3 V)2
Output Coding
DMID
Temp
Full
25°C
25°C
Full
Full
Full
Test
Level
IV
V
V
II
II
V
AD6645ASQ-80/AD6645ASV-80
Min Typ
Max
0.4
10
2.5
CMOS
2.85 DVCC − 2
0.2 0.5
Twos complement
DVCC/2
AD6645ASQ-105/AD6645ASV-105
Min Typ
Max
0.4
10
2.5
CMOS
2.85 DVCC − 2
0.2
Twos complement
DVCC/2
0.5
Unit
V p-p
pF
V
V
V
1 All ac specifications tested by driving ENCODE and ENCODE differentially.
2 Digital output logic levels: DVCC = 3.3 V, CLOAD = 10 pF. Capacitive loads >10 pF degrades performance.
AC SPECIFICATIONS
All ac specifications tested by driving ENCODE and ENCODE differentially. AVCC = 5 V, DVCC = 3.3 V; ENCODE, ENCODE, TMIN and
TMAX at rated speed grade, unless otherwise noted.
Table 3.
Parameter
SNR
Analog Input @ −1 dBFS
SINAD
Analog Input @ −1 dBFS
WORST HARMONIC (SECOND OR THIRD)
Analog Input @ −1 dBFS
Temp
Test
Level
AD6645ASQ-80/
AD6645ASV-80
Min Typ Max
AD6645ASQ-105/
AD6645ASV-105
Min Typ Max
Unit
Conditions
25°C V
Full II
25°C I
Full II
25°C V
25°C V
75.0
72.5 74.5
72.0 73.5
73.0
72.0
75.0
72.5 74.5
72.0 73.5
73.0
72.0
dB At 15.5 MHz
dB At 30.5 MHz
dB At 37.7 MHz
dB At 70.0 MHz
dB At 150.0 MHz
dB At 200.0 MHz
25°C V
Full II
25°C I
Full V
25°C V
25°C V
75.0
72.5 74.5
73.0
68.5
62.5
75.0
72.5 74.5
73.0
67.5
62.5
dB At 15.5 MHz
dB At 30.5 MHz
dB At 37.7 MHz
dB At 70.0 MHz
dB At 150.0 MHz
dB At 200.0 MHz
25°C V
Full II
25°C I
Full V
25°C V
25°C V
93.0
85.0 93.0
89.0
70.0
63.5
93.1
85.0 93.0
87.0
70.0
63.5
dBc At 15.5 MHz
dBc At 30.5 MHz
dBc At 37.7 MHz
dBc At 70.0 MHz
dBc At 150.0 MHz
dBc At 200.0 MHz
Rev. D | Page 4 of 24


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