80 MSPS/105 MSPS A/D Converter
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THEORY OF OPERATION
The AD6645 ADC employs a three-stage subrange architecture.
This design approach achieves the required accuracy and speed
while maintaining low power and small die size.
As shown in the functional block diagram (see Figure 1), the
AD6645 has complementary analog input pins, AIN and AIN.
Each analog input is centered at 2.4 V and should swing ±0.55 V
around this reference (see Figure 32). Because AIN and AIN are
180° out of phase, the differential analog input signal is 2.2 V p-p.
Both analog inputs are buffered prior to the first track-and-hold,
TH1. The high state of the encode pulse places TH1 in hold
mode. The held value of TH1 is applied to the input of a 5-bit
coarse ADC1. The digital output of ADC1 drives a 5-bit digital-
to-analog converter, DAC1. DAC1 requires 14 bits of precision
that is achieved through laser trimming. The output of DAC1 is
subtracted from the delayed analog signal at the input of TH3 to
generate a first residue signal. TH2 provides an analog pipeline
delay to compensate for the digital delay of ADC1.
The first residual signal is applied to a second conversion stage
consisting of a 5-bit ADC2, a 5-bit DAC2, and a pipeline TH4.
The second DAC requires 10 bits of precision, which is met by
the process with no trim. The input to TH5 is a second residual
signal generated by subtracting the quantized output of DAC2
from the first residual signal held by TH4. TH5 drives a final
The digital outputs from ADC1, ADC2, and ADC3 are added
together and corrected in the digital error correction logic to
generate the final output data. The result is a 14-bit parallel
digital CMOS-compatible word, coded as twos complement.
APPLYING THE AD6645
Encoding the AD6645
The AD6645 encode signal must be a high quality, extremely
low phase noise source to prevent degradation of performance.
Maintaining 14-bit accuracy places a premium on encode clock
phase noise. SNR performance can easily degrade by 3 dB to
4 dB with 70 MHz analog input signals when using a high jitter
clock source. See the AN-501 application note, Aperture
Uncertainty and ADC System Performance, for complete details.
For optimum performance, the AD6645 must be clocked
differentially. The encode signal is usually ac-coupled into the
ENCODE and ENCODE pins via a transformer or capacitors.
These pins are biased internally and require no additional bias.
Figure 38 shows one preferred method for clocking the AD6645.
The clock source (low jitter) is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the transformer secondary limit excessive amplitude
swings from the clock into the AD6645 to approximately 0.8 V p-p
differential. This helps to prevent the large voltage swings of the
clock from feeding through to other portions of the AD6645
and limits the noise presented to the encode inputs.
Figure 38. Crystal Clock Oscillator, Differential Encode
If a low jitter clock is available, another option is to ac-couple a
differential ECL/PECL signal to the encode input pins, as
shown in Figure 39. The MC100EL16 (or same family) from
ON Semiconductor offers excellent jitter performance.
Figure 39. Differential ECL for Encode
Driving the Analog Inputs
As with most new high speed, high dynamic range ADCs, the
analog input to the AD6645 is differential. Differential inputs
improve on-chip performance as signals are processed through
attenuation and gain stages. Most of the improvement is a result
of differential analog stages having high rejection of even-order
harmonics. There are also benefits at the PCB level. First,
differential inputs have high common-mode rejection of stray
signals, such as ground and power noise. Second, they provide
good rejection of common-mode signals, such as local oscillator
The AD6645 analog input voltage range is offset from ground
by 2.4 V. Each analog input connects through a 500 Ω resistor to
the 2.4 V bias voltage and to the input of a differential buffer (see
Figure 32). The resistor network on the input properly biases the
followers for maximum linearity and range. Therefore, the analog
source driving the AD6645 should be ac-coupled to the input pins.
Because the differential input impedance of the AD6645 is 1 kΩ,
the analog input power requirement is only −2 dBm, simplifying
the driver amplifier in many cases. To take full advantage of this
high input impedance, a 20:1 RF transformer is required. This is a
large ratio and can result in unsatisfactory performance. In this
case, a lower step-up ratio can be used. The recommended method
for driving the differential analog input of the AD6645 is to use
a 4:1 RF transformer. For example, if RT is set to 60.4 Ω and RS is set
to 25 Ω, along with a 4:1 impedance ratio transformer, the input
would match to a 50 Ω source with a full-scale drive of 4.8 dBm.
Series resistors (RS) on the secondary side of the transformer
should be used to isolate the transformer from the A/D.
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