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AD664 Datasheet
Monolithic 12-Bit Quad DAC

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a
Monolithic
12-Bit Quad DAC
AD664
FEATURES
Four Complete Voltage Output DACs
Data Register Readback Feature
“Reset to Zero” Override
Multiplying Operation
Double-Buffered Latches
Surface Mount and DIP Packages
MIL-STD-883 Compliant Versions Available
APPLICATIONS
Automatic Test Equipment
Robotics
Process Control
Disk Drives
Instrumentation
Avionics
PRODUCT DESCRIPTION
The AD664 is four complete 12-bit, voltage-output DACs on
one monolithic IC chip. Each DAC has a double-buffered input
latch structure and a data readback function. All DAC read and
write operations occur through a single microprocessor-compatible
I/O port.
The I/O port accommodates 4-, 8- or 12-bit parallel words al-
lowing simple interfacing with a wide variety of microprocessors.
A reset to zero control pin is provided to allow a user to simulta-
neously reset all DAC outputs to zero, regardless of the contents
of the input latch. Any one or all of the DACs may be placed in
a transparent mode allowing immediate response by the outputs
to the input data.
The analog portion of the AD664 consists of four DAC cells,
four output amplifiers, a control amplifier and switches. Each
DAC cell is an inverting R-2R type. The output current from
each DAC is switched to the on-board application resistors and
output amplifier. The output range of each DAC cell is pro-
grammed through the digital I/O port and may be set to unipo-
lar or bipolar range, with a gain of one or two times the reference
voltage. All DACs are operated from a single external reference.
The functional completeness of the AD664 results from the
combination of Analog Devices’ BiMOS II process, laser-trimmed
thin-film resistors and double-level metal interconnects.
PRODUCT HIGHLIGHTS
1. The AD664 provides four voltage-output DACs on one chip
offering the highest density 12-bit D/A function available.
2. The output range of each DAC is fully and independently
programmable.
3. Readback capability allows verification of contents of the in-
ternal data registers.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
PIN CONFIGURATIONS
44-Pin Package
28-Pin DIP Package
4. The asynchronous RESET control returns all D/A outputs
to zero volts.
5. DAC-to-DAC matching performance is specified and tested.
6. Linearity error is specified to be 1/2 LSB at room tempera-
ture and 3/4 LSB maximum for the K, B and T grades.
7. DAC performance is guaranteed to be monotonic over the
full operating temperature range.
8. Readback buffers have tristate outputs.
9. Multiplying-mode operation allows use with fixed or vari-
able, positive or negative external references.
10. The AD664 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD664/883B data sheet for detailed
specifications.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/461-3113


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Monolithic 12-Bit Quad DAC

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AD664* Product Page Quick Links
Last Content Update: 11/01/2016
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• AD664: Monolithic 12-Bit Quad DAC Data Sheet
• AD664: Military Data Sheet
Reference Materials
Solutions Bulletins & Brochures
• Digital to Analog Converters ICs Solutions Bulletin
Design Resources
• AD664 Material Declaration
• PCN-PDN Information
• Quality And Reliability
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AD664 Datasheet
Monolithic 12-Bit Quad DAC

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AD664–SPECIFICATIONS (VLL = +5 V, VCC = +15 V, VEE = –15 V, VREF = +10 V, TA = +25؇C
unless otherwise noted)
Model
JN/JP/AD/AJ/SD
Min Typ Max
KN/KP/BD/BJ/BE/TD/TE
Min Typ
Max
Units
RESOLUTION
12 12
ANALOG OUTPUT
Voltage Range1
UNI Versions
BIP Versions
Output Current
Load Resistance
Load Capacitance
Short-Circuit Current
0
VEE + 2.02
5
2
25
VCC – 2.02
VCC – 2.02
500
40
ACCURACY
Gain Error
Unipolar Offset
Bipolar Zero3
Linearity Error4
Linearity TMIN to TMAX
Differential Linearity
Differential Linearity TMIN to TMAX
Gain Error Drift
Unipolar 0 V to +10 V Mode
Bipolar –5 V to +5 V Mode
Bipolar –10 V to +10 V Mode
Unipolar Offset Drift
Unipolar 0 V to +10 V Mode
Bipolar Zero Drift
Bipolar –5 V to +5 V Mode
Bipolar –10 V to +10 V Mode
–7 ± 3 7
–2 ± 1/2 2
–3 ± 3/4 3
–3/4 ± 1/2 3/4
–1 ± 3/4 1
–3/4 3/4
Monotonic @ All Temperatures
–12 ± 7 12
–12 ± 7 12
–12 ± 7 12
–3 ± l.5 3
–12 ± 7 12
–12 ± 7 12
REFERENCE INPUT
Input Resistance
Voltage Range6
POWER REOUIREMENTS
VLL
ILL
@ VIH, VIL = 5 V, 0 V
@ VIH, VIL = 2.4 V, 0.4 V
VCC /VEE
ICC
IEE
Total Power
1.3
VEE + 2.02
4.5
؎11.4
5.0
0.1
3
12
15
400
2. 6
VCC – 2.02
5.5
1
6
؎16.5
15
19
525
ANALOG GROUND CURRENT7
–600
± 400 +600
MATCHING PERFORMANCE
Gain8
Offset9
Bipolar Zero10
Linearity11
–6 ± 3 6
–2 ± 1/2 2
–3 ± 1 3
–1.5 ± 1/2 1.5
CROSSTALK
Analog
Digital
–90
–60
DYNAMIC PERFORMANCE (RL = 2 k, CL = 500 pF)
Settling Time to ± 1/2 LSB
OffBitsOn, GAIN = 1, VREF = 10
Settling Time to ± 1/2 LSB
–10VREF 10 V, GAIN = 1, Bits On
Glitch Impulse
8 10
10
500
MULTIPLYING MODE PERFORMANCE
Reference Feedthrough @ 1 kHz
Reference –3 dB Bandwidth
–75
70
POWER SUPPLY GAIN SENSITIVITY
11.4 VVCC16.5 V
–16.5 VVEE–11.4 V
4.5 VVLL5.5 V
± 2 ؎5
± 2 ؎5
± 2 ؎5
* * Bits
*
*
*
*
*
* Volts
* Volts
mA
k
* pF
* mA
–5 ± 2
5
–1 ± 1/4 1
–2 ± 1/2 2
–1/2 ± 1/4
1/2
–3/4 ± 1/2
3/4
–1/2 1/2
Monotonic @ All Temperatures
LSB
LSB
LSB
LSB
LSB
LSB
–10 ± 5
–10 ± 5
–10 ± 5
10 ppm of FSR5/°C
10 ppm of FSR/°C
10 ppm of FSR/°C
–2 ± l
2 ppm of FSR/°C
–10 ± 5
–10 ± 5
10 ppm of FSR/°C
10 ppm of FSR/°C
* * k
* * Volts
**
*
*
*
*
*
*
**
* Volts
* mA
* mA
* Volts
* mA
* mA
* mW
* µA
–4 ± 2 4 LSB
–1 ± 1/4 1 LSB
–2 ± 1 2 LSB
–1 ± 1/2 1 LSB
* dB
* dB
* * µs
* µs
* nV-sec
* dB
* kHz
* * ppm/%
* * ppm/%
* * ppm/%
–2– REV. D


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Monolithic 12-Bit Quad DAC

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AD664
Model
JN/JP/AD/AJ/SD
Min Typ Max
KN/KP/BD/BJ/BE/TD/TE
Min Typ
Max
Units
DIGITAL INPUTS
VIH
VIL
Data Inputs
IIH @ VIN = VLL
IIL @ VIN = DGND
CS/DS0/DS1/RST/RD/LS
IIH @ VIN = VLL
IIL @ VIN = VLL
MS/TR12
IIH @ VIN = VLL
IIL @ VIN = DGND
QS0/QSl/QS2 l2
IIH @ VIN = VLL
IIL @ VIN = DGND
2.0 *
0 0.8 *
–10 ± 1 10
–10 ± 1 10
**
**
–10 ± 1 10
–10 ± 1 10
**
**
–10 5 10
–10 –5 0
**
**
–10 5 10
–10 ± 1 10
**
**
Volts
* Volts
* µA
* µA
* µA
* µA
* µA
* µA
* µA
* µA
DIGITAL OUTPUTS
VOL @ 1.6 mA Sink
VOH @ 0.5 mA Source
0.4
2.4 *
* Volts
Volts
TEMPERATURE RANGE
JN/JP/KN/KP
AD/AJ/BD/BJ/BE
SD/TD/TE
0 +70 *
– 40 +85 *
–55
+125
*
* °C
* °C
* °C
NOTES
1A minimum power supply of ±12.0 V is required for 0 V to +10 V and ±10 V operation. A minimum power supply of ±11.4 V is required for –5 V to +5 V operation.
2For VCC < +12 V and VEE > –12 V. Voltage not to exeeed 10 V maximum.
3Bipolar zero error is the difference from the ideal output (0 volts) and the actual output voltage with code 100 000 000 000 applied to the inputs.
4Linearity error is defined as the maximum deviation of the actual DAC output from the ideal output (a straight line drawn from 0 to F.S. – 1 LSB).
5FSR means Full-Scale Range and is 20 V for ± 10 V range and 10 V for ± 5 V range.
6A minimum power supply of ± 12.0 V is required for a 10 V reference voltage.
7Analog Ground Current is input code dependent.
8Gain error matching is the largest difference in gain error between any two DACs in one package.
9Offset error matching is the largest difference in offset error between any two DACs in one package.
10Bipolar zero error matching is the largest difference in bipolar zero error between any two DACs in one package.
11Linearity error matching is the difference in the worst ease linearity error between any two DACs in one package.
1244-pin versions only.
*Specifications same as JN/JP/AD/AJ/SD.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
ABSOLUTE MAXIMUM RATINGS*
VLL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +7 V
VCC to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +18 V
VEE to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 V to 0 V
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C, 10 sec
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . –1 V to +1 V
Reference Input . . . . . . . . . . . . . . . . . . VREF ≤ ± 10 V and VREF
(VCC – 2 V, VEE + 2 V)
VCC to VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +36 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Outputs . . . . . . . . . . . . . . . . . . . . . Indefinite Shorts to
VCC, VLL, VEE and GND
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Unused devices must be stored in conductive foam
or shunts. The protective foam should be discharged to the destination socket before devices are
removed.
REV. D
–3–
WARNING!
ESD SENSITIVE DEVICE


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AD664
Figure 1a. 44-Pin Block Diagram
FUNCTIONAL DESCRIPTION
The AD664 combines four complete 12-bit voltage output D/A
converters with a fast, flexible digital input/output port on one
monolithic chip. It is available in two forms, a 44-pin version
shown in Figure 1a and a 28-pin version shown in Figure 1b.
tions. This register may also be read back to check its contents.
A RESET-TO-ZERO feature allows all DACs to be reset to 0
volts out by strobing a single pin.
44-Pin Versions
Each DAC offers flexibility, accuracy and good dynamic perfor-
mance. The R-2R structure is fabricated from thin-film resistors
which are laser-trimmed to achieve 1/2 LSB linearity and guar-
anteed monotonicity. The output amplifier combines the best
features of the bipolar and MOS devices to achieve good dy-
namic performance and low offset. Settling time is under 10 µs
and each output can drive a 5 mA, 500 pF load. Short-circuit
protection allows indefinite shorts to VLL, VCC, VEE and GND.
The output and span resistor pins are available separately. This
feature allows a user to insert current-boosting elements to in-
crease the drive capability of the system, as well as to overcome
parasitics.
Digital circuitry is implemented in CMOS logic. The fast, low
power, digital interface allows the AD664 to be interfaced with
most microprocessors. Through this interface, the wide variety
of features on each chip may be accessed. For example, the in-
put data for each DAC is programmed by way of 4-, 8-, 12- or
16-bit words. The double-buffered input structure of this latch
allows all four DACs to be updated simultaneously. A readback
feature allows the internal registers to be read back through the
same digital port, as either 4-, 8- or 12-bit words. When dis-
abled, the readback drivers are placed in a high impedance
(tristate) mode. A TRANSPARENT mode allows the input data
to pass straight through both ranks of input registers and appear
at the DAC with a minimum of delay. One D/A may be placed
in the transparent mode at a time, or all four may be made
transparent at once. The MODE SELECT feature allows the
output range and mode of the DACs to be selected via the data
bus inputs. An internal mode select register stores the selec-
Figure 1b. 28-Pin Block Diagram
28-Pin Versions
The 28-pin versions are dedicated versions of the 44-pin
AD664. Each offers a reduced set of features from those offered
in the 44-pin version. This accommodates the reduced number
of package pins available. Data is written and read with 12-bit
words only. Output range and mode select functions are also
not available in 28-pin versions. As an alternative, users specify
either the UNI (unipolar, 0 to VREF) models or the BIP (bipolar,
–VREF to VREF) models depending on the application require-
ments. Finally, the transparent mode is not available on the
28-pin versions.
–4– REV. D


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