AD627 Datasheet
Rail-to-Rail Instrumentation Amplifier

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Data Sheet
Micropower, Single- and Dual-Supply,
Rail-to-Rail Instrumentation Amplifier
AD627
FEATURES
Micropower, 85 μA maximum supply current
Wide power supply range (+2.2 V to ±18 V)
Easy to use
Gain set with one external resistor
Gain range 5 (no resistor) to 1000
Higher performance than discrete designs
Rail-to-rail output swing
High accuracy dc performance
0.03% typical gain accuracy (G = +5) (AD627A)
10 ppm/°C typical gain drift (G = +5)
125 μV maximum input offset voltage (AD627B dual supply)
200 μV maximum input offset voltage (AD627A dual supply)
1 μV/°C maximum input offset voltage drift (AD627B)
3 μV/°C maximum input offset voltage drift (AD627A)
10 nA maximum input bias current
Noise: 38 nV/√Hz RTI noise at 1 kHz (G = +100)
Excellent ac specifications
AD627A: 77 dB minimum CMRR (G = +5)
AD627B: 83 dB minimum CMRR (G = +5)
80 kHz bandwidth (G = +5)
135 μs settling time to 0.01% (G = +5, 5 V step)
APPLICATIONS
4 mA to 20 mA loop-powered applications
Low power medical instrumentation—ECG, EEG
Transducer interfacing
Thermocouple amplifiers
Industrial process controls
Low power data acquisition
Portable battery-powered instruments
GENERAL DESCRIPTION
The AD627 is an integrated, micropower instrumentation
amplifier that delivers rail-to-rail output swing on single and
dual (+2.2 V to ±18 V) supplies. The AD627 provides excellent
ac and dc specifications while operating at only 85 μA maximum.
The AD627 offers superior flexibility by allowing the user to set
the gain of the device with a single external resistor while con-
forming to the 8-lead industry-standard pinout configuration.
With no external resistor, the AD627 is configured for a gain of 5.
With an external resistor, it can be set to a gain of up to 1000.
A wide supply voltage range (+2.2 V to ±18 V) and micropower
current consumption make the AD627 a perfect fit for a wide
range of applications. Single-supply operation, low power
consumption, and rail-to-rail output swing make the AD627
Rev. E
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
RG 1
AD627
8 RG
–IN 2
7 +VS
+IN 3
6 OUTPUT
–VS 4
5 REF
Figure 1. 8-Lead PDIP (N) and SOIC_N (R)
100
90
80
AD627
70
60
50
TRADITIONAL
40 LOW POWER
DISCRETE DESIGN
30
20
10
0
1 10 100 1k 10k
FREQUENCY (Hz)
Figure 2. CMRR vs. Frequency, ±5 VS, Gain = +5
ideal for battery-powered applications. Its rail-to-rail output
stage maximizes dynamic range when operating from low
supply voltages. Dual-supply operation (±15 V) and low power
consumption make the AD627 ideal for industrial applications,
including 4 mA to 20 mA loop-powered systems.
The AD627 does not compromise performance, unlike other
micropower instrumentation amplifiers. Low voltage offset,
offset drift, gain error, and gain drift minimize errors in the
system. The AD627 also minimizes errors over frequency by
providing excellent CMRR over frequency. Because the CMRR
remains high up to 200 Hz, line noise and line harmonics are
rejected.
The AD627 provides superior performance, uses less circuit
board area, and costs less than micropower discrete designs.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2007−2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com


AD627 Datasheet
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AD627* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
View a parametric search of comparable parts
Evaluation Kits
• AD62x, AD822x, AD842x Series InAmp Evaluation Board
Documentation
Application Notes
• AN-1401: Instrumentation Amplifier Common-Mode
Range: The Diamond Plot
• AN-244: A User's Guide to I.C. Instrumentation Amplifiers
• AN-245: Instrumentation Amplifiers Solve Unusual Design
Problems
• AN-282: Fundamentals of Sampled Data Systems
• AN-589: Ways to Optimize the Performance of a
Difference Amplifier
• AN-671: Reducing RFI Rectification Errors in In-Amp
Circuits
Data Sheet
• AD627: Micropower, Single and Dual Supply Rail-to-Rail
Instrumentation Amplifier Data Sheet
Technical Books
• A Designer's Guide to Instrumentation Amplifiers, 3rd
Edition, 2006
User Guides
• UG-261: Evaluation Boards for the AD62x, AD822x and
AD842x Series
Tools and Simulations
• In-Amp Error Calculator
• AD627A SPICE Macro-Model
Reference Materials
Technical Articles
• Auto-Zero Amplifiers
• High-performance Adder Uses Instrumentation Amplifiers
• Input Filter Prevents Instrumentation-amp RF-Rectification
Errors
• MS-2178: Discussion Between CareFusion and Analog
Devices: Optimizing Performance and Lowering Power in
an EEG Amplifer
• Protecting Instrumentation Amplifiers
• The AD8221 - Setting a New Industry Standard for
Instrumentation Amplifiers
Design Resources
• AD627 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
View all AD627 EngineerZone Discussions
Sample and Buy
Visit the product page to see pricing options
Technical Support
Submit a technical question or find your regional support
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* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
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frequently modified.


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AD627
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Single Supply ................................................................................. 3
Dual Supply ................................................................................... 5
Dual and Single Supplies ............................................................. 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 14
Using the AD627 ............................................................................ 15
Basic Connections ...................................................................... 15
Setting the Gain .......................................................................... 15
Data Sheet
Reference Terminal .................................................................... 16
Input Range Limitations in Single-Supply Applications....... 16
Output Buffering ........................................................................ 17
Input and Output Offset Errors................................................ 17
Make vs. Buy: A Typical Application Error Budget............... 18
Errors Due to AC CMRR .......................................................... 19
Ground Returns for Input Bias Currents ................................ 19
Layout and Grounding .............................................................. 20
Input Protection ......................................................................... 21
RF Interference ........................................................................... 21
Applications Circuits...................................................................... 22
Classic Bridge Circuit ................................................................ 22
4 mA to 20 mA Single-Supply Receiver .................................. 22
Thermocouple Amplifier .......................................................... 22
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
12/13—Rev. D to Rev. E
Change to Voltage Noise, 1 kHz Parameter, Table 3 .................... 6
Changes to Figure 35...................................................................... 14
Change to Equation 3, Input Range Limitations in Single-
Supply Applications Section.......................................................... 16
Changes to Table 8.......................................................................... 17
Changes to Figure 40...................................................................... 17
Change to Table 9 ........................................................................... 18
Change to 4 mA to 20 mA Single-Supply Receiver Section ..... 22
11/07—Rev. C to Rev. D
Changes to Features.......................................................................... 1
Changes to Figure 29 to Figure 34 Captions ............................... 13
Changes to Setting the Gain Section............................................ 15
Changes to Input Range Limitations in Single-Supply
Applications Section....................................................................... 16
Changes to Table 7.......................................................................... 17
Changes to Figure 41...................................................................... 18
11/05—Rev. B to Rev. C
Updated Format..................................................................Universal
Added Pin Configurations and Function
Descriptions Section .........................................................................8
Change to Figure 33 ....................................................................... 13
Updated Outline Dimensions....................................................... 24
Changes to Ordering Guide .......................................................... 24
Rev. A to Rev. B
Changes to Figure 4 and Table I, Resulting Gain column......... 11
Change to Figure 9 ......................................................................... 13
Rev. E | Page 2 of 24


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Data Sheet
AD627
SPECIFICATIONS
SINGLE SUPPLY
Typical at 25°C single supply, VS = 3 V and 5 V, and RL = 20 kΩ, unless otherwise noted.
Table 1.
Parameter
GAIN
Gain Range
Gain Error1
G = +5
G = +10
G = +100
G = +1000
Nonlinearity
G = +5
G = +100
Gain vs. Temperature1
G = +5
G > +5
VOLTAGE OFFSET
Input Offset, VOSI2
Over Temperature
Average TC
Output Offset, VOSO
Over Temperature
Average TC
Offset Referred to the
Input vs. Supply (PSRR)
G = +5
G = +10
G = +100
G = +1000
INPUT CURRENT
Input Bias Current
Over Temperature
Average TC
Input Offset Current
Over Temperature
Average TC
INPUT
Input Impedance
Differential
Common-Mode
Input Voltage Range3
Common-Mode Rejection
Ratio3 DC to 60 Hz with
1 kΩ Source Imbalance
G = +5
G = +5
OUTPUT
Output Swing
Short-Circuit Current
Conditions
G = +5 + (200 kΩ/RG)
VOUT = (−VS) + 0.1 to (+VS) − 0.15
VCM = VREF = +VS/2
VS = 2.2 V to 36 V
VREF = VS/2
VS = 3 V, VCM = 0 V to 1.9 V
VS = 5 V, VCM = 0 V to 3.7 V
RL = 20 kΩ
RL = 100 kΩ
Short circuit to ground
AD627A
Min Typ
5
0.03
0.15
0.15
0.50
10
20
10
−75
50
0.1
2.5
86 100
100 120
110 125
110 125
3
20
0.3
1
(−VS) − 0.1
20||2
20||2
77 90
77 90
(−VS) + 25
(−VS) + 7
±25
AD627B
Max Min
Typ Max
Unit
1000
5
1000
V/V
0.10
0.01 0.06
%
0.35
0.10 0.25
%
0.35
0.10 0.25
%
0.70
0.25 0.35
%
100
10 100
ppm
100
20 100
ppm
20
10 20
ppm/°C
−75 ppm/°C
250
445
3
1000
1650
10
25 150
215
0.1 1
500
1150
2.5 10
µV
µV
µV/°C
µV
µV
µV/°C
86
100
110
110
10
15
1
2
100
120
125
125
3 10
15
20
0.3 1
2
1
dB
dB
dB
dB
nA
nA
pA/°C
nA
nA
pA/°C
(+VS) − 1
(−VS) − 0.1
20||2
20||2
(+VS) – 1
GΩ||pF
GΩ||pF
V
83 96
83 96
dB
dB
(+VS) − 70 (−VS) + 25
(+VS) − 25 (−VS) + 7
(+VS) − 70 mV
(+VS) − 25 mV
±25 mA
Rev. E | Page 3 of 24


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AD627
Data Sheet
Parameter
DYNAMIC RESPONSE
Small Signal −3 dB
Bandwidth
G = +5
G = +100
G = +1000
Slew Rate
Settling Time to 0.01%
G = +5
G = +100
Settling Time to 0.01%
G = +5
G = +100
Overload Recovery
Conditions
VS = 3 V, 1.5 V output step
VS = 5 V, 2.5 V output step
50% input overload
Min
AD627A
Typ
Max
80
3
0.4
+0.05/−0.07
65
290
85
330
3
AD627B
Min Typ Max
+0.05/−0.07
80
3
0.4
65
290
85
330
3
1 Does not include effects of External Resistor RG.
2 See Table 8 for total RTI errors.
3 See the Using the AD627 section for more information on the input range, gain range, and common-mode range.
Unit
kHz
kHz
kHz
V/µs
µs
µs
µs
µs
µs
Rev. E | Page 4 of 24


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Data Sheet
AD627
DUAL SUPPLY
Typical at 25°C dual supply, VS = ±5 V and ±15 V, and RL = 20 kΩ, unless otherwise noted.
Table 2.
Parameter
GAIN
Gain Range
Gain Error1
G = +5
G = +10
G = +100
G = +1000
Nonlinearity
G = +5
G = +100
Gain vs. Temperature1
G = +5
G > +5
VOLTAGE OFFSET
Input Offset, VOSI2
Over Temperature
Average TC
Output Offset, VOSO
Over Temperature
Average TC
Offset Referred to the Input
vs. Supply (PSRR)
G = +5
G = +10
G = +100
G = +1000
INPUT CURRENT
Input Bias Current
Over Temperature
Average TC
Input Offset Current
Over Temperature
Average TC
INPUT
Input Impedance
Differential
Common Mode
Input Voltage Range3
Common-Mode Rejection
Ratio3 DC to 60 Hz with
1 kΩ Source Imbalance
G = +5 to +1000
G = +5 to +1000
OUTPUT
Output Swing
Short-Circuit Current
Conditions
G = +5 + (200 kΩ/RG)
VOUT = (−VS) + 0.1 to
(+VS) − 0.15
Min
5
VS = ±5 V/±15 V
VS = ±5 V/±15 V
Total RTI error =
VOSI + VOSO/G
VCM = VREF = 0 V
AD627A
Typ
0.03
0.15
0.15
0.50
10/25
10/15
10
–75
25
0.1
2.5
86 100
100 120
110 125
110 125
2
20
0.3
5
VS = ±1.1 V to ±18 V
(−VS) − 0.1
20||2
20||2
VS = ±5 V, VCM =
−4 V to +3.0 V
VS = ±15 V, VCM =
−12 V to +10.9 V
77
77
90
90
RL = 20 kΩ
RL = 100 kΩ
Short circuit to ground
(−VS) + 25
(−VS) + 7
±25
Max
1000
0.10
0.35
0.35
0.70
100
100
20
Min
5
200
395
3
1000
1700
10
10
15
1
5
86
100
110
110
AD627B
Typ
0.01
0.10
0.10
0.25
10/25
10/15
10
−75
25
0.1
2.5
100
120
125
125
2
20
0.3
5
(+VS) − 1
(−VS) − 0.1
20||2
20||2
83 96
83 96
(+VS) − 70 (−VS) + 25
(+VS) − 25 (−VS) + 7
±25
Max
1000
0.06
0.25
0.25
0.35
100
100
20
125
190
1
500
1100
10
10
15
1
5
Unit
V/V
%
%
%
%
ppm
ppm
ppm/°C
ppm/°C
µV
µV
µV/°C
µV
µV
µV/°C
dB
dB
dB
dB
nA
nA
pA/°C
nA
nA
pA/°C
(+VS) − 1
GΩ||pF
GΩ||pF
V
dB
dB
(+VS) − 70
(+VS) − 25
mV
mV
mA
Rev. E | Page 5 of 24


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AD627
Data Sheet
Parameter
DYNAMIC RESPONSE
Small Signal −3 dB
Bandwidth
G = +5
G = +100
G = +1000
Slew Rate
Settling Time to 0.01%
G = +5
G = +100
Settling Time to 0.01%
G = +5
G = +100
Overload Recovery
Conditions
Min
VS = ±5 V,
+5 V output step
VS = ±15 V,
+15 V output step
50% input overload
AD627A
Typ
Max
Min
80
3
0.4
+0.05/−0.06
135
350
330
560
3
330
560
3
1 Does not include effects of External Resistor RG.
2 See Table 8 for total RTI errors.
3 See the Using the AD627 section for more information on the input range, gain range, and common-mode range.
AD627B
Typ
Max
Unit
80
3
0.4
+0.05/−0.06
135
350
kHz
kHz
kHz
V/µs
µs
µs
µs
µs
µs
DUAL AND SINGLE SUPPLIES
Table 3.
Parameter
NOISE
Voltage Noise, 1 kHz
Input, Voltage Noise, eni
Output, Voltage Noise, eno
RTI, 0.1 Hz to 10 Hz
G = +5
G = +1000
Current Noise
0.1 Hz to 10 Hz
REFERENCE INPUT
RIN
Gain to Output
Voltage Range1
POWER SUPPLY
Operating Range
Quiescent Current
Over Temperature
TEMPERATURE RANGE
For Specified Performance
Conditions
Total RTI Noise = (eni )2 + (eno /G)2
f = 1 kHz
RG = ∞
Dual supply
Single supply
AD627A
AD627B
Min Typ
Max Min Typ
Max Unit
38
177
1.2
0.56
50
1.0
125
1
±1.1
2.2
60
200
−40
38
177
1.2
0.56
50
1.0
125
1
±18 ±1.1
36 2.2
85 60
200
+85 −40
nV/√Hz
nV/√Hz
µV p-p
µV p-p
fA/√Hz
pA p-p
kΩ
±18 V
36 V
85 µA
nA/°C
+85 °C
1 See Using the AD627 section for more information on the reference terminal, input range, gain range, and common-mode range.
Rev. E | Page 6 of 24


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Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Supply Voltage
Internal Power Dissipation1
PDIP (N-8)
SOIC_N (R-8)
−IN, +IN
Common-Mode Input Voltage
Differential Input Voltage (+IN − (−IN))
Output Short-Circuit Duration
Storage Temperature Range (N, R)
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Rating
±18 V
1.3 W
0.8 W
−VS − 20 V to +VS + 20 V
−VS − 20 V to +VS + 20 V
+VS − (−VS)
Indefinite
−65°C to +125°C
−40°C to +85°C
300°C
1 Specification is for device in free air:
8-lead PDIP package: θJA = 90°C/W.
8-lead SOIC_N package: θJA = 155°C/W.
AD627
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. E | Page 7 of 24


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AD627
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Data Sheet
RG 1
8 RG
–IN 2 AD627 7 +VS
+IN
3
TOP VIEW
(Not to Scale)
6 OUTPUT
–VS 4
5 REF
Figure 3. 8-Lead PDIP Pin Configuration
RG 1
8 RG
–IN 2 AD627 7 +VS
TOP VIEW
+IN 3 (Not to Scale) 6 OUTPUT
–VS 4
5 REF
Figure 4. 8-Lead SOIC_N Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic Description
1 RG External Gain Setting Resistor. Place gain setting resistor across RG pins to set the gain.
2 −IN Negative Input.
3 +IN Positive Input.
4 −VS Negative Voltage Supply Pin.
5 REF Reference Pin. Drive with low impedance voltage source to level shift the output voltage.
6 OUTPUT Output Voltage.
7 +VS Positive Supply Voltage.
8 RG External Gain Setting Resistor. Place gain setting resistor across RG pins to set the gain.
Rev. E | Page 8 of 24


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Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
At 25°C, VS = ±5 V, RL = 20 kΩ, unless otherwise noted.
100
90
80
70
60
GAIN = +5
50
40
30
GAIN = +100
20
GAIN = +1000
10
0
1 10 100 1k 10k 100k
FREQUENCY (Hz)
Figure 5. Voltage Noise Spectral Density vs. Frequency
100
90
80
70
60
50
40
30
20
10
0
1
10 100
1k 10k
FREQUENCY (Hz)
Figure 6. Current Noise Spectral Density vs. Frequency
–3.2
–3.0
–2.8
–2.6
–2.4
–2.2
–2.0
–15
–10 –5
0
5
COMMON-MODE INPUT (V)
10
Figure 7. Input Bias Current vs. CMV, VS = ±15 V
15
AD627
–5.5
–5.0
–4.5
–4.0
–3.5
VS = +5V
VS = ±5V
–3.0
–2.5
–2.0
VS = ±15V
–1.5
–60
–40 –20
0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 8. Input Bias Current vs. Temperature
140
65.5
64.5
63.5
62.5
61.5
60.5
59.5
0
5 10 15 20 25 30 35
TOTAL POWER SUPPLY VOLTAGE (V)
Figure 9. Supply Current vs. Supply Voltage
40
V+
(V+) –1
(V+) –2
(V+) –3
VS = ±1.5V
VS = ±2.5V
SOURCING
VS = ±15V
VS = ±5V
(V–) +2
SINKING
(V–) +1
V–
0
VS = ±2.5V
VS = ±1.5V
VS = ±5V
VS = ±15V
5 10 15 20
OUTPUT CURRENT (mA)
Figure 10. Output Voltage Swing vs. Output Current
25
Rev. E | Page 9 of 24


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AD627
500mV
100
1s
10
Figure 11. 0.1 Hz to 10 Hz Current Noise (0.71 pA/DIV)
20mV
100
11ss
10
Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise (400 nV/DIV), G = +5
2V
100
1s
10
Figure 13. 0.1 Hz to 10 Hz RTI Voltage Noise (200 nV/DIV), G = +1000
Data Sheet
120
110
100
90
80
70
60
50
40
30
20
10
G = +1000
G = +100
G = +5
100 1k
FREQUENCY (Hz)
10k
Figure 14. Positive PSRR vs. Frequency, ±5 V
100k
100
90
80
70
60
50
40
30
20
10
0
10
G = +1000
G = +100
G = +5
100 1k
FREQUENCY (Hz)
10k
Figure 15. Negative PSRR vs. Frequency, ±5 V
100k
120
110
100
G = +1000
90
80 G = +100
70
60 G = +5
50
40
30
20
10
100 1k
FREQUENCY (Hz)
10k
100k
Figure 16. Positive PSRR vs. Frequency (VS = 5 V, 0 V)
Rev. E | Page 10 of 24


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Data Sheet
10
1
0.1 5
10
100
GAIN (V/V)
1k
Figure 17. Settling Time to 0.01% vs. Gain for a 5 V Step at Output, RL = 20 kΩ,
CL = 100 pF, VS = ±5 V
1mV
1V
50µs
AD627
400
300
200
100
0
0 ±2 ±4 ±6 ±8 ±10
OUTPUT PULSE (V)
Figure 20. Settling Time to 0.01% vs. Output Swing, G = +5, RL = 20 kΩ,
CL = 100 pF
200µV
1V
100µs
Figure 18. Large Signal Pulse Response and Settling Time, G = –5, RL = 20 kΩ,
CL = 100 pF (1.5 mV = 0.01%)
1mV
1V
50µs
Figure 21. Large Signal Pulse Response and Settling Time, G = –100,
RL = 20 kΩ, CL = 100 pF (100 µV = 0.01%)
200µV
1V
500µs
Figure 19. Large Signal Pulse Response and Settling Time, G = −10,
RL = 20 kΩ, CL = 100 pF (1.0 mV = 0.01%)
Figure 22. Large Signal Pulse Response and Settling Time, G = –1000,
RL = 20 kΩ, CL = 100 pF (10 µV = 0.01%)
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120
110
100
90
G = +1000
80
70
G = +100
60
50
G = +5
40
30
20
10
0
1 10 100 1k 10k 100k
FREQUENCY (Hz)
Figure 23. CMRR vs. Frequency, ±5 VS (CMV = 200 mV p-p)
70
60 G = +1000
50
G = +100
40
30
G = +10
20
10 G = +5
0
–10
–20
–30
100
1k 10k
FREQUENCY (Hz)
100k
Figure 24. Gain vs. Frequency (VS = 5 V, 0 V), VREF = 2.5 V
CH2 20mV
A 20µs 288mV EXT1
CH2 20mV
Data Sheet
A 20µs 286mV EXT1
Figure 26. Small Signal Pulse Response, G = +10, RL = 20 kΩ, CL = 50 pF
CH2 20mV
A 100µs 286mV EXT1
Figure 27. Small Signal Pulse Response, G = +100, RL = 20 kΩ, CL = 50 pF
CH2 50mV
A 1ms 286mV EXT1
Figure 25. Small Signal Pulse Response, G = +5, RL = 20 kΩ, CL = 50 pF
Figure 28. Small Signal Pulse Response, G = +1000, RL = 20 kΩ, CL = 50 pF
Rev. E | Page 12 of 24


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Data Sheet
20µV/DIV
200µV/DIV
AD627
VOUT
0.5V/DIV
Figure 29. Gain Nonlinearity, Negative Input,
VS = ±2.5 V, G = +5 (4 ppm/DIV)
40µV/DIV
VOUT
0.5V/DIV
Figure 30. Gain Nonlinearity, Negative Input,
VS = ±2.5 V, G = +100 (8 ppm/DIV)
40µV/DIV
VOUT
3V/DIV
Figure 31. Gain Nonlinearity, Negative Input,
VS = ±15 V, G = +5 (1.5 ppm/DIV)
VOUT
3V/DIV
Figure 32. Gain Nonlinearity, Negative Input,
VS = ±15 V, G = +100 (7 ppm/DIV)
200µV/DIV
VOUT
3V/DIV
Figure 33. Gain Nonlinearity, Negative Input,
VS = ±15 V, G = +5 (7 ppm/DIV)
200µV/DIV
VOUT
3V/DIV
Figure 34. Gain Nonlinearity, Negative Input,
VS = ±15 V, G = +100 (7 ppm/DIV)
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Data Sheet
THEORY OF OPERATION
The AD627 is a true instrumentation amplifier, built using two
feedback loops. Its general properties are similar to those of the
classic two-op-amp instrumentation amplifier configuration but
internally the details are somewhat different. The AD627 uses a
modified current feedback scheme, which, coupled with interstage
feedforward frequency compensation, results in a much better
common-mode rejection ratio (CMRR) at frequencies above
dc (notably the line frequency of 50 Hz to 60 Hz) than might
otherwise be expected of a low power instrumentation amplifier.
In Figure 35, A1 completes a feedback loop that, in conjunction
with V1 and R5, forces a constant collector current in Q1. Assume
that the gain-setting resistor (RG) is not present. Resistors R2
and R1 complete the loop and force the output of A1 to be equal
to the voltage on the inverting terminal with a gain of nearly
1.25. A2 completes a nearly identical feedback loop that forces
a current in Q2 that is nearly identical to that in Q1; A2 also
provides the output voltage. When both loops are balanced, the
gain from the noninverting terminal to VOUT is equal to 5,
whereas the gain from the output of A1 to VOUT is equal to −4.
The inverting terminal gain of A1 (1.25) times the gain of A2
(−4) makes the gain from the inverting and noninverting
terminals equal.
The differential mode gain is equal to 1 + R4/R3, nominally 5,
and is factory trimmed to 0.01% final accuracy. Adding an
external gain setting resistor (RG) increases the gain by an
amount equal to (R4 + R1)/RG. The output voltage of the
AD627 is given by
VOUT = [VIN(+) – VIN(−)] × (5 + 200 kΩ/RG) + VREF
(1)
Laser trims are performed on R1 through R4 to ensure that
their values are as close as possible to the absolute values in the
gain equation. This ensures low gain error and high common-
mode rejection at all practical gains.
R1
100kΩ
REF
+VS
–IN 2kΩ
–VS
EXTERNAL GAIN RESISTOR
RG R4
100kΩ
R2
25kΩ
R3
25kΩ
+VS
Q1 Q2 2kΩ +IN
A1
R5
200kΩ V1
0.1V
–VS
A2
R6
200kΩ
Figure 35. Simplified Schematic
OUTPUT
–VS
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Data Sheet
USING THE AD627
BASIC CONNECTIONS
Figure 36 shows the basic connection circuit for the AD627.
The +VS and −VS terminals connect to the power supply. The
supply can be either bipolar (VS = ±1.1 V to ±18 V) or single
supply (−VS = 0 V, +VS = 2.2 V to 36 V). Capacitively decouple
the power supplies close to the power pins of the device. For
best results, use surface-mount 0.1 µF ceramic chip capacitors.
The input voltage can be single-ended (tie either −IN or +IN to
ground) or differential. The difference between the voltage on the
inverting and noninverting pins is amplified by the programmed
gain. The gain resistor programs the gain as described in the
Setting the Gain and Reference Terminal sections. Basic
connections are shown in Figure 36. The output signal appears
as the voltage difference between the output pin and the
externally applied voltage on the REF pin, as shown in Figure 37.
AD627
SETTING THE GAIN
The gain of the AD627 is resistor programmed by RG, or, more
precisely, by whatever impedance appears between Pin 1 and Pin 8.
The gain is set according to
Gain = 5 + (200 kΩ/RG) or RG = 200 kΩ/(Gain − 5) (2)
Therefore, the minimum achievable gain is 5 (for 200 kΩ/
(Gain − 5)). With an internal gain accuracy of between 0.05%
and 0.7%, depending on gain and grade, a 0.1% external gain
resistor is appropriate to prevent significant degradation of the
overall gain error. However, 0.1% resistors are not available in a
wide range of values and are quite expensive. Table 6 shows
recommended gain resistor values using 1% resistors. For all
gains, the size of the gain resistor is conservatively chosen as the
closest value from the standard resistor table that is higher than
the ideal value. This results in a gain that is always slightly less
than the desired gain, thereby preventing clipping of the signal
at the output due to resistor tolerance.
The internal resistors on the AD627 have a negative temperature
coefficient of −75 ppm/°C maximum for gains > 5. Using a
gain resistor that also has a negative temperature coefficient
of −75 ppm/°C or less tends to reduce the overall gain drift of
the circuit.
+VS
+1.1V TO +18V
0.1µF
+VS
+2.2V TO +36V
0.1µF
+IN
VIN RG
–IN
RG
OUTPUT
RG REF
0.1µF
+IN
VOUT
REF (INPUT)
VIN RG
–IN
RG
OUTPUT
RG REF
VOUT
REF (INPUT)
–1.1V TO –18V
–VS
GAIN = 5 + (200kΩ/RG)
Figure 36. Basic Connections for Single and Dual Supplies
VCM
V+
VDIFF
2
+IN
VDIFF
2
–IN
V–
REF
100kΩ
+VS
–IN 2kΩ
–VS
EXTERNAL GAIN RESISTOR
RG
25kΩ
25kΩ
100kΩ
+VS
Q1 Q2 2kΩ +IN
A1 –VS
A2
OUTPUT
200kΩ 0.1V VA
200kΩ
Figure 37. Amplifying Differential Signals with a Common-Mode Component
–VS
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Table 6. Recommended Values of Gain Resistors
Desired Gain
1% Standard Table
Value of RG
Resulting Gain
5∞
5.00
6 200 kΩ
6.00
7 100 kΩ
7.00
8 68.1 kΩ
7.94
9 51.1 kΩ
8.91
10 40.2 kΩ
9.98
15 20 kΩ
15.00
20 13.7 kΩ
19.60
25 10 kΩ
25.00
30 8.06 kΩ
29.81
40 5.76 kΩ
39.72
50 4.53 kΩ
49.15
60 3.65 kΩ
59.79
70 3.09 kΩ
69.72
80 2.67 kΩ
79.91
90 2.37 kΩ
89.39
100 2.1 kΩ
100.24
200 1.05 kΩ
195.48
500 412 Ω
490.44
1000
205 Ω
980.61
REFERENCE TERMINAL
The reference terminal potential defines the zero output voltage
and is especially useful when the load does not share a precise
ground with the rest of the system. It provides a direct means of
injecting a precise offset to the output. The reference terminal is
also useful when amplifying bipolar signals, because it provides
a virtual ground voltage.
The AD627 output voltage is developed with respect to the poten-
tial on the reference terminal; therefore, tying the REF pin to the
appropriate local ground solves many grounding problems. For
optimal CMR, tie the REF pin to a low impedance point.
INPUT RANGE LIMITATIONS IN SINGLE-SUPPLY
APPLICATIONS
In general, the maximum achievable gain is determined by the
available output signal range. However, in single-supply applica-
tions where the input common-mode voltage is nearly or equal
to 0, some limitations on the gain can be set. Although the
Specifications section nominally defines the input, output, and
reference pin ranges, the voltage ranges on these pins are
mutually interdependent. Figure 37 shows the simplified
schematic of the AD627, driven by a differential voltage (VDIFF)
that has a common-mode component, VCM. The voltage on the
A1 op amp output is a function of VDIFF, VCM, the voltage on the
REF pin, and the programmed gain. This voltage is given by
VA1 = 1.25 (VCM + 0.5 V) − 0.25 VREF VDIFF (25 kΩ/RG + 0.625) (3)
Data Sheet
The voltage on A1 can also be expressed as a function of the
actual voltages on the –IN and +IN pins (V− and V+) such that
VA1 = 1.25 ((V−) + 0.5 V) − 0.25 VREF − ((V+) − (V−)) 25 kΩ/RG (4)
The output of A1 is capable of swinging to within 50 mV of the
negative rail and to within 200 mV of the positive rail. It is clear,
from either Equation 3 or Equation 4, that an increasing VREF
(while it acts as a positive offset at the output of the AD627)
tends to decrease the voltage on A1. Figure 38 and Figure 39
show the maximum voltages that can be applied to the REF pin
for a gain of 5 for both the single-supply and dual-supply cases.
5
4
3
2
MAXIMUM VREF
1
0
–1
MINIMUM VREF
–2
–3
–4
–5
–6 –5 –4 –3 –2 –1 0 1 2 3 4
VIN(–) (V)
Figure 38. Reference Input Voltage vs. Negative Input Voltage,
VS = ±5 V, G = +5
5
MAXIMUM VREF
4
3
2
MINIMUM VREF
1
0
–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VIN(–) (V)
Figure 39. Reference Input Voltage vs. Negative Input Voltage,
VS = 5 V, G = +5
Raising the input common-mode voltage increases the voltage
on the output of A1. However, in single-supply applications
where the common-mode voltage is low, a differential input
voltage or a voltage on REF that is too high can drive the output
of A1 into the ground rail. Some low-side headroom is added
because both inputs are shifted upwards by about 0.5 V (that is,
by the VBE of Q1 and Q2). Use Equation 3 and Equation 4 to
check whether the voltage on Amplifier A1 is within its
operating range.
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Data Sheet
AD627
Table 7. Maximum Gain for Low Common-Mode, Single-Supply Applications
VIN REF Pin Supply Voltage RG (1% Tolerance)
±100 mV, VCM = 0 V
2 V 5 V to 15 V
28.7 kΩ
±50 mV, VCM = 0 V
2 V 5 V to 15 V
10.7 kΩ
±10 mV, VCM = 0 V
2 V 5 V to 15 V
1.74 kΩ
V− = 0 V, V+ = 0 V to 1 V
1 V 10 V to 15 V 78.7 kΩ
V− = 0 V, V+ = 0 mV to 100 mV 1 V
5 V to 15 V
7.87 kΩ
V− = 0 V, V+ = 0 mV to 10 mV 1 V
5 V to 15 V
787 Ω
Resulting Maximum Gain
12.0
23.7
119.9
7.5
31
259.1
Output Swing WRT 0 V
0.8 V to 3.2 V
0.8 V to 3.2 V
0.8 V to 3.2 V
1 V to 8.5 V
1 V to 4.1 V
1 V to 3.6 V
Table 8. RTI Error Sources
Maximum Total RTI Offset Error (μV)
Gain
AD627A
AD627B
+5 450
250
+10 350
200
+20 300
175
+50 270
160
+100
270
155
+500
252
151
+1000
251
151
Maximum Total RTI Offset Drift (μV/°C)
AD627A
AD627B
53
42
3.5 1.5
3.2 1.2
3.1 1.1
31
31
Total RTI Noise (nV/√Hz)
AD627A/AD627B
52
42
39
38
38
38
38
Table 7 gives values for the maximum gain for various single-
supply input conditions. The resulting output swings refer to
0 V. To maximize the available gain and output swing, set the
voltages on the REF pins to either 2 V or 1 V. In most cases,
there is no advantage to increasing the single supply to greater
than 5 V (the exception is an input range of 0 V to 1 V).
OUTPUT BUFFERING
The AD627 is designed to drive loads of 20 kΩ or greater but
can deliver up to 20 mA to heavier loads at lower output voltage
swings (see Figure 10). If more than 20 mA of output current is
required at the output, buffer the AD627 output with a precision
op amp, such as the OP113. Figure 40 shows this for a single
supply. This op amp can swing from 0 V to 4 V on its output
while driving a load as small as 600 Ω.
+VS
0.1µF
0.1µF
VIN RG
AD627
REF
0.1µF
OP113
0.1µF
–VS
–VS
Figure 40. Output Buffering
VOUT
INPUT AND OUTPUT OFFSET ERRORS
The low errors of the AD627 are attributed to two sources,
input and output errors. The output error is divided by G when
referred to the input. In practice, input errors dominate at high
gains and output errors dominate at low gains. The total offset
error for a given gain is calculated as
Total Error RTI = Input Error + (Output Error/Gain) (5)
Total Error RTO = (Input Error × G) + Output Error (6)
RTI offset errors and noise voltages for different gains are listed
in Table 8.
Rev. E | Page 17 of 24


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MAKE vs. BUY: A TYPICAL APPLICATION ERROR
BUDGET
The example in Figure 41 serves as a good comparison between
the errors associated with an integrated and a discrete in-amp
implementation. A ±100 mV signal from a resistive bridge
(common-mode voltage = 2.5 V) is amplified. This example
compares the resulting errors from a discrete two-op-amp
instrumentation amplifier and the AD627. The discrete
implementation uses a four-resistor precision network
(1% match, 50 ppm/°C tracking).
Data Sheet
The errors associated with each implementation (see Table 9)
show the integrated in-amp to be more precise at both ambient
and overtemperature. Note that the discrete implementation is
more expensive, primarily due to the relatively high cost of the
low drift precision resistor network.
The input offset current of the discrete instrumentation amplifier
implementation is the difference in the bias currents of the two-
op amplifiers, not the offset currents of the individual op amps.
In addition, although the values of the resistor network are chosen
so that the inverting and noninverting inputs of each op amp
see the same impedance (about 350 Ω), the offset current of
each op amp adds another error that must be characterized.
+5V
350Ω
350Ω
+5V
350Ω
350Ω
±100mV
RG
40.2kΩ
1%
+10ppm/°C
AD627A
VOUT
+2.5V
LT10781SB
1/2
+5V
LT10781SB
1/2 VOUT
3.15kΩ*
+2.5V
350Ω*
350Ω* 3.15kΩ*
AD627A GAIN = 9.98 (5+(200kΩ/R G))
HOMEBREW IN-AMP, G = +10
*1% RESISTOR MATCH, 50ppm/°C TRACKING
Figure 41. Make vs. Buy
Table 9. Make vs. Buy Error Budget
Error Source
ABSOLUTE ACCURACY at TA = 25°C
Total RTI Offset Voltage, mV
Input Offset Current, nA
Internal Offset Current
(Homebrew Only)
CMRR, dB
Gain
DRIFT TO 85°C
Gain Drift, ppm/°C
Total RTI Offset Voltage, mV/°C
Input Offset Current, pA/°C
AD627 Circuit Calculation
(250 μV + (1000 μV/10))/100 mV
1 nA × 350 Ω/100 mV
Not applicable
77 dB141 ppm × 2.5 V/100 mV
0.35% + 1%
(−75 + 10) ppm/°C × 60°C
(3.0 μV/°C + (10 μV/°C/10)) ×
60°C/100 mV
(16 pA/°C × 350 Ω × 60°C)/100 mV
Homebrew Circuit Calculation
(180 μV × 2)/100 mV
20 nA × 350 Ω/100 mV
0.7 nA × 350 Ω/100 mV
(1% match × 2.5 V)/10/100 mV
1% match
Total Absolute Error
50 ppm/°C × 60°C
(2 × 3.5 μV/°C × 60°C)/100 mV
(33 pA/°C × 350 Ω × 60°C)/100 mV
Total Drift Error
Grand Total Error
Total Error
AD627
(ppm)
Total Error
Homebrew
(ppm)
3,500
3.5
3,531
13,500
20,535
3,600
70
2.45
25,000
10,000
38,672
3,900
2,600
3.5
6,504
27,039
3,000
4,200
7
7,207
45,879
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Data Sheet
ERRORS DUE TO AC CMRR
In Table 9, the error due to common-mode rejection results
from the common-mode voltage from the bridge 2.5 V. The
ac error due to less than ideal common-mode rejection cannot
be calculated without knowing the size of the ac common-mode
voltage (usually interference from 50 Hz/60 Hz mains frequencies).
A mismatch of 0.1% between the four gain setting resistors
determines the low frequency CMRR of a two-op-amp
instrumentation amplifier. The plot in Figure 43 shows the
practical results of resistor mismatch at ambient temperature.
The CMRR of the circuit in Figure 42 (Gain = +11) was
measured using four resistors with a mismatch of nearly 0.1%
(R1 = 9999.5 Ω, R2 = 999.76 Ω, R3 = 1000.2 Ω, R4 = 9997.7 Ω).
As expected, the CMRR at dc was measured at about 84 dB
(calculated value is 85 dB). However, as frequency increases,
CMRR quickly degrades. For example, a 200 mV p-p harmonic
of the mains frequency at 180 Hz would result in an output
voltage of about 800 µV. To put this in context, a 12-bit data
acquisition system, with an input range of 0 V to 2.5 V, has an
LSB weighting of 610 µV.
By contrast, the AD627 uses precision laser trimming of internal
resistors, along with patented CMR trimming, to yield a higher
dc CMRR and a wider bandwidth over which the CMRR is flat
(see Figure 23).
+5V
VIN–
VIN+
A1
1/2
OP296
A2
1/2
OP296
VOUT
R1
9999.5Ω
–5V
R2
999.76Ω
R3
1000.2Ω
R4
9997.7Ω
Figure 42. 0.1% Resistor Mismatch Example
120
110
100
90
80
70
60
50
40
30
20
1 10 100 1k 10k 100k
FREQUENCY (Hz)
Figure 43. CMRR over Frequency of Discrete In-Amp in Figure 42
AD627
GROUND RETURNS FOR INPUT BIAS CURRENTS
Input bias currents are dc currents that must flow to bias the
input transistors of an amplifier. They are usually transistor base
currents. When amplifying floating input sources, such as
transformers or ac-coupled sources, there must be a direct dc
path into each input so that the bias current can flow. Figure 44,
Figure 45, and Figure 46 show how to provide a bias current
path for the cases of, respectively, transformer coupling, a
thermocouple application, and capacitive ac-coupling.
In dc-coupled resistive bridge applications, providing this path
is generally not necessary because the bias current simply flows
from the bridge supply through the bridge and into the amplifier.
However, if the impedance that the two inputs see are large, and
differ by a large amount (>10 kΩ), the offset current of the input
stage causes dc errors compatible with the input offset voltage of
the amplifier.
–INPUT
RG
+INPUT
+VS
2
7
1
AD627 6
85
34
REFERENCE
LOAD
–VS
VOUT
TO POWER
SUPPLY
GROUND
Figure 44. Ground Returns for Bias Currents with Transformer Coupled Inputs
–INPUT
2
1
+VS
7
RG
+INPUT
AD627 6
85
34
REFERENCE
LOAD
–VS
VOUT
TO POWER
SUPPLY
GROUND
Figure 45. Ground Returns for Bias Currents with Thermocouple Inputs
–INPUT
2
1
+VS
7
RG
8
+INPUT
3
100kΩ
AD627 6
5
4 REFERENCE
LOAD
–VS
VOUT
TO POWER
SUPPLY
GROUND
Figure 46. Ground Returns for Bias Currents with AC-Coupled Inputs
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LAYOUT AND GROUNDING
The use of ground planes is recommended to minimize the
impedance of ground returns (and hence, the size of dc errors).
To isolate low level analog signals from a noisy digital environment,
many data acquisition components have separate analog and
digital ground returns (see Figure 47). Return all ground pins
from mixed-signal components, such as analog-to-digital
converters, through the high quality analog ground plane.
Digital ground lines of mixed-signal components should also
be returned through the analog ground plane. This may seem
to break the rule of separating analog and digital grounds;
however, in general, there is also a requirement to keep the
voltage difference between digital and analog grounds on a
converter as small as possible (typically, <0.3 V). The increased
noise, caused by the digital return currents of the converter
flowing through the analog ground plane, is generally negligible.
To maximize isolation between analog and digital, connect the
ground planes back at the supplies.
Data Sheet
If there is only one power supply available, it must be shared by
both digital and analog circuitry. Figure 48 shows how to minimize
interference between the digital and analog circuitry. As in the
previous case, use separate analog and digital ground planes or
use reasonably thick traces as an alternative to a digital ground
plane. Connect the ground planes at the ground pin of the power
supply. Run separate traces (or power planes) from the power
supply to the supply pins of the digital and analog circuits. Ideally,
each device should have its own power supply trace, but they
can be shared by multiple devices if a single trace is not used to
route current to both digital and analog circuitry.
ANALOG POWER SUPPLY
+5V –5V GND
0.1µF 0.1µF
0.1µF
DIGITAL POWER SUPPLY
GND +5V
0.1µF
7
24
AD627
35
6
1 6 14
4 VIN1
VDD AGND DGND
3 VIN2 ADC AD7892-2
12 AGND VDD
MICRO-
PROCESSOR
Figure 47. Optimal Grounding Practice for a Bipolar Supply Environment with Separate Analog and Digital Supplies
POWER SUPPLY
5V GND
0.1µF
7
24
AD627
35
6
0.1µF
0.1µF
1
VDD
4 VIN
ADC
AGND DGND
AD7892-2
12 VDD DGND
MICRO-
PROCESSOR
Figure 48. Optimal Ground Practice in a Single-Supply Environment
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Data Sheet
INPUT PROTECTION
As shown in the simplified schematic (see Figure 35), both the
inverting and noninverting inputs are clamped to the positive
and negative supplies by ESD diodes. In addition, a 2 kΩ series
resistor on each input provides current limiting in the event of
an overvoltage. These ESD diodes can tolerate a maximum
continuous current of 10 mA. So an overvoltage (that is, the
amount by which the input voltage exceeds the supply voltage)
of ±20 V can be tolerated. This is true for all gains, and for
power on and off. This last case is particularly important
because the signal source and amplifier can be powered
separately.
If the overvoltage is expected to exceed 20 V, use additional
external series current-limiting resistors to keep the diode
current below 10 mA.
RF INTERFERENCE
All instrumentation amplifiers can rectify high frequency out-
of-band signals. Once rectified, these signals appear as dc offset
errors at the output. The circuit in Figure 49 provides good RFI
suppression without reducing performance within the pass
band of the instrumentation amplifier. Resistor R1 and
Capacitor C1 (and likewise, R2 and C2) form a low-pass RC
filter that has a –3 dB BW equal to
f = 1/(2π(R1 × C1))
(7)
Using the component values shown in Figure 49, this filter has
a –3 dB bandwidth of approximately 8 kHz. Resistor R1 and
Resistor R2 were selected to be large enough to isolate the circuit
input from the capacitors but not large enough to significantly
increase circuit noise. To preserve common-mode rejection in
the amplifier pass band, Capacitor C1 and Capacitor C2 must
be 5% mica units, or low cost 20% units can be tested and binned
to provide closely matched devices.
AD627
Capacitor C3 is needed to maintain common-mode rejection at
low frequencies. R1/R2 and C1/C2 form a bridge circuit whose
output appears across the input pins of the in-amp. Any mismatch
between C1 and C2 unbalances the bridge and reduces common-
mode rejection. C3 ensures that any RF signals are common
mode (the same on both in-amp inputs) and are not applied
differentially. This second low-pass network, R1 + R2 and C3,
has a −3 dB frequency equal to
1/(2π((R1 + R2) × C3))
+VS
(8)
R1
20k
1%
C1
1000pF
5%
+IN
R2 C3
20k0.022µF
1%
–IN
C2
1000pF
5%
0.33µF 0.01µF
RG AD627
VOUT
REFERENCE
0.33µF 0.01µF
–VS
Figure 49. Circuit to Attenuate RF Interference
Using a C3 value of 0.022 μF, as shown in Figure 49, the −3 dB
signal bandwidth of this circuit is approximately 200 Hz. The
typical dc offset shift over frequency is less than 1 mV and the
RF signal rejection of the circuit is better than 57 dB. To increase
the 3 dB signal bandwidth of this circuit, reduce the value of
Resistor R1 and Resistor R2. The performance is similar to that
when using 20 kΩ resistors, except that the circuitry preceding
the in-amp must drive a lower impedance load.
When building a circuit like that shown in Figure 49, use a PC
board with a ground plane on both sides. Make all component
leads as short as possible. Resistor R1 and Resistor R2 can be
common 1% metal film units, but Capacitor C1 and Capacitor C2
must be ±5% tolerance devices to avoid degrading the common-
mode rejection of the circuit. Either the traditional 5% silver mica
units or Panasonic ±2% PPS film capacitors are recommended.
Rev. E | Page 21 of 24


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Rail-to-Rail Instrumentation Amplifier

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AD627
APPLICATIONS CIRCUITS
CLASSIC BRIDGE CIRCUIT
Figure 50 shows the AD627 configured to amplify the signal
from a classic resistive bridge. This circuit works in dual-supply
mode or single-supply mode. Typically, the same voltage that
powers the instrumentation amplifiers excites the bridge.
Connecting the bottom of the bridge to the negative supply of
the instrumentation amplifiers (usually 0 V, −5 V, −12 V, or
−15 V), sets up an input common-mode voltage that is
optimally located midway between the supply voltages. It is
also appropriate to set the voltage on the REF pin to midway
between the supplies, especially if the input signal is bipolar.
However, the voltage on the REF pin can be varied to suit the
application. For example, the REF pin is tied to the VREF pin of
an analog-to-digital converter (ADC) whose input range is
(VREF ± VIN). With an available output swing on the AD627 of
(−VS + 100 mV) to (+VS − 150 mV), the maximum programmable
gain is simply this output range divided by the input range.
+VS
0.1µF
VDIFF RG =G2A00INkΩ–5
AD627
0.1µF
–VS
Figure 50. Classic Bridge Circuit
VOUT
VREF
Data Sheet
4 mA TO 20 mA SINGLE-SUPPLY RECEIVER
Figure 51 shows how a signal from a 4 mA to 20 mA transducer
can be interfaced to the ADuC812, a 12-bit ADC with an
embedded microcontroller. The signal from a 4 mA to 20 mA
transducer is single-ended, which initially suggests the need for
a simple shunt resistor to convert the current to a voltage at the
high impedance analog input of the converter. However, any
line resistance in the return path (to the transducer) adds a
current dependent offset error; therefore, the current must be
sensed differentially.
In this example, a 24.9 Ω shunt resistor generates a maximum
differential input voltage to the AD627 of between 100 mV
(for 4 mA in) and 500 mV (for 20 mA in). With no gain resistor
present, the AD627 amplifies the 500 mV input voltage by a
factor of 5, to 2.5 V, the full-scale input voltage of the ADC. The
zero current of 4 mA corresponds to a code of 819 and the LSB
size is 4.88 μA.
THERMOCOUPLE AMPLIFIER
Because the common-mode input range of the AD627 extends
0.1 V below ground, it is possible to measure small differential
signals that have a low, or no, common-mode component.
Figure 51 shows a thermocouple application where one side of
the J-type thermocouple is grounded.
Over a temperature range from −200°C to +200°C, the J-type
thermocouple delivers a voltage ranging from −7.890 mV to
+10.777 mV. A programmed gain on the AD627 of 100 (RG =
2.1 kΩ) and a voltage on the AD627 REF pin of 2 V result in the
output voltage of the AD627 ranging from 1.110 V to 3.077 V
relative to ground. For a different input range or different
voltage on the REF pin, it is important to verify that the voltage
on Internal Node A1 (see Figure 37) is not driven below
ground. This can be checked using the equations in the Input
Range Limitations in Single-Supply Applications section.
5V
0.1µF
J-TYPE
THERMOCOUPLE
RG
2.1kΩ
AD627
REF
VOUT
VREF
Figure 51. Amplifying Bipolar Signals with Low Common-Mode Voltage
Rev. E | Page 22 of 24


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Rail-to-Rail Instrumentation Amplifier

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Data Sheet
5V
0.1µF
4–20mA
TRANSDUCER
LINE
IMPEDANCE
4–20mA
24.9Ω
G = +5 AD627
REF
AD627
5V 5V
0.1µF
0.1µF
VREF
AIN 0
to AIN 7
AVDD
DVDD
ADuC812
MICROCONVERTER®
AGND
DGND
Figure 52. 4 mA to 20 mA Receiver Circuit
Rev. E | Page 23 of 24


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Rail-to-Rail Instrumentation Amplifier

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AD627
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
85
14
0.210 (5.33)
MAX
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.100 (2.54)
BSC
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.060 (1.52)
MAX
0.015
(0.38)
MIN
0.015 (0.38)
GAUGE
SEATING
PLANE
PLANE
0.005 (0.13)
MIN
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.430 (10.92)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 53. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body (N-8)
Dimensions shown in inches (and millimeters)
Data Sheet
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
8
1
5
6.20 (0.2441)
4 5.80 (0.2284)
0.25 (0.0098)
0.10 (0.0040)
1.27 (0.0500)
BSC
1.75 (0.0688)
1.35 (0.0532)
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196) 45°
0.25 (0.0099)
1.27 (0.0500)
0.25 (0.0098) 0.40 (0.0157)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 54. 8-Lead Small Standard Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters (and inches)
ORDERING GUIDE
Model1
AD627ANZ
AD627AR
AD627AR-REEL
AD627AR-REEL7
AD627ARZ
AD627ARZ-R7
AD627ARZ-RL
AD627BNZ
AD627BR
AD627BR-REEL
AD627BR-REEL7
AD627BRZ
AD627BRZ-RL
AD627BRZ-R7
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
1 Z = RoHS Compliant part.
Package Description
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Small Standard Outline [SOIC_N]
8-Lead Small Standard Outline [SOIC_N]
8-Lead Small Standard Outline [SOIC_N]
8-Lead Small Standard Outline [SOIC_N]
8-Lead Small Standard Outline [SOIC_N]
8-Lead Small Standard Outline [SOIC_N]
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Small Standard Outline [SOIC_N]
8-Lead Small Standard Outline [SOIC_N]
8-Lead Small Standard Outline [SOIC_N]
8-Lead Small Standard Outline [SOIC_N]
8-Lead Small Standard Outline [SOIC_N]
8-Lead Small Standard Outline [SOIC_N]
Package Option
N-8
R-8
R-8
R-8
R-8
R-8
R-8
N-8
R-8
R-8
R-8
R-8
R-8
R-8
©2007−2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00782-0-12/13(E)
Rev. E | Page 24 of 24



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