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ICS551 Datasheet
1 TO 4 CLOCK BUFFER

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1 TO 4 CLOCK BUFFER
DATASHEET
ICS551
Description
The ICS551 is a low cost, high-speed single input to
four output clock buffer. Part of IDT’s ClockBlocksTM
family, this is our lowest cost, small clock buffer.
See the ICS552-02B for monolithic dual version of the
ICS551 in a 20 pin QSOP.
IDT makes many non-PLL and PLL based low skew
output devices as well as Zero Delay Buffers to
synchronize clocks. Contact IDT for all of your clocking
needs.
Features
Low skew (250 ps) outputs
Pb-free packaging
Low cost clock buffer
Packaged in 8-pin SOIC
Input/Output clock frequency up to 160 MHz
Non-inverting output clock
Ideal for networking clocks
Operating Voltages of 3.3 and 5.0 V
Output Enable mode tri-states outputs
Advanced, low power CMOS process
Commercial and industrial temperature versions
Block Diagram
ICLK
Q1
Q2
Q3
Q4
Output Enable
IDT™ 1 TO 4 CLOCK BUFFER
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1 TO 4 CLOCK BUFFER

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ICS551
1 TO 4 CLOCK BUFFER
Pin Assignment
ICLK
Q1
Q2
Q3
1
2
3
4
8 OE
7 VDD
6 GND
5 Q4
8 Pin (150 mil) SOIC
FAN OUT BUFFER
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
ICLK
Q1
Q2
Q3
Q4
GND
VDD
OE
Pin
Type
Pin Description
Input Clock input. Internal pull-up resistor.
Output Clock output 1.
Output Clock output 2.
Output Clock output 3.
Output Clock output 4.
Power Connect to ground.
Power Connect to 3.3 V or 5.0 V.
Input Output Enable. Tri-states outputs when low. Internal pull-up resistor.
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of
0.01 µF should be connected between VDD on pin 7 and GND on pin 6, as close to the device as possible.
A 33series terminating resistor may be used on each clock output if the trace is longer than 1 inch.
IDT™ 1 TO 4 CLOCK BUFFER
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1 TO 4 CLOCK BUFFER

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ICS551
1 TO 4 CLOCK BUFFER
FAN OUT BUFFER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS551. These ratings, which
are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature, Commercial
Ambient Operating Temperature, Industrial
Storage Temperature
Junction Temperature
Soldering Temperature
Rating
7V
-0.5 V to VDD+0.5 V
0 to +70° C
-40 to +85° C
-65 to +150° C
125° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
-40
+3.0
Typ.
Max.
+85
+5.5
Units
°C
V
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ICS551
1 TO 4 CLOCK BUFFER
FAN OUT BUFFER
DC Electrical Characteristics
VDD=3.3 V ±10% , Ambient temperature -40 to +85 ° C, unless stated otherwise
Parameter
Symbol Conditions
Min. Typ.
Operating Voltage
VDD
3.0
Input High Voltage, ICLK
Input Low Voltage, ICLK
Input High Voltage, OE
Input Low Voltage, OE
Output High Voltage
Output Low Voltage
Output High Voltage (CMOS
Level)
VIH
VIL
VIH
VIL
VOH
VOL
VOH
Note 1
Note 1
IOH = -25 mA
IOL = 25 mA
IOH = -12 mA
VDD/2+0.7
2
2.4
VDD-0.4
Operating Supply Current
IDD No load, 135 MHz
18
Nominal Output Impedance
Internal Pull-up Resistor
Input Capacitance
Short Circuit Current
ZO
RPU
CIN
IOS
OE
OE pin
20
500
5
±50
Max. Units
3.6 V
3.8 V
VDD/2-0.7 V
VDD
V
0.8 V
V
0.4 V
V
mA
k
pF
mA
VDD = 5 V ±10% , Ambient temperature -40 to +85 ° C, unless stated otherwise
Parameter
Symbol Conditions
Min.
Typ.
Operating Voltage
VDD
4.5
Input High Voltage, ICLK
Input Low Voltage, ICLK
Input High Voltage, OE
Input Low Voltage, OE
Output High Voltage
Output Low Voltage
Output High Voltage (CMOS
Level)
VIH
VIL
VIH
VIL
VOH
VOL
VOH
Note 1
Note 1
IOH = -35 mA
IOL = 35 mA
IOH = -12 mA
VDD/2+1
2
2.4
VDD-0.4
Operating Supply Current
IDD No load, 135 MHz
35
Nominal Output Impedance
ZO
Internal Pull-up Resistor
RPU OE
Input Capacitance
CIN OE pin
Short Circuit Current
IOS
Notes: 1. Nominal switching threshold is VDD/2.
20
220
5
±80
Max. Units
5.5 V
5.5 V
VDD/2-1 V
VDD
V
0.8 V
V
0.4 V
V
mA
k
pF
mA
IDT™ 1 TO 4 CLOCK BUFFER
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1 TO 4 CLOCK BUFFER

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ICS551
1 TO 4 CLOCK BUFFER
FAN OUT BUFFER
AC Electrical Characteristics
VDD = 3.3 V ±10%, Ambient Temperature -40 to +85 ° C, unless stated otherwise
Parameter
Symbol
Conditions
Min. Typ.
Input Frequency
0
Output Frequency
15 pF load, Note 4
Output Clock Rise Time
Output Clock Fall Time
Propagation Delay
tOR
tOF
Note 1
0.8 to 2.0 V
2.0 to 0.8 V
135 MHz
24
Output to Output Skew
Note 2 Rising edges at VDD/2
Max.
160
160
1.0
1.0
8
250
Units
MHz
MHz
ns
ns
ns
ps
VDD = 5 V ±10%, Ambient Temperature -40 to +85 ° C, unless stated otherwise
Parameter
Symbol
Conditions
Min.
Input Frequency
0
Output Frequency
15 pF load, Note 4
Output Clock Rise Time
Output Clock Fall Time
Propagation Delay
tOR
tOF
Note 1
0.8 to 2.0 V
2.0 to 0.8 V
135 MHz
1.5
Output to Output Skew
Note 2 Rising edges at VDD/2
Typ.
3
Max.
135
135
1.0
1.0
6
250
Units
MHz
MHz
ns
ns
ns
ps
Notes:
1. With rail to rail input clock.
2. Between any 2 outputs with equal loading.
3. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock
generators.
4. With external series resistor of 33positioned close to each output pin.
Marking Diagram (ICS551MLF)
Marking Diagram (ICS551MLN)
85
85
551MLF
######
YYWW
551MLN
######
YYWW
14
14
IDT™ 1 TO 4 CLOCK BUFFER
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REV P 051310



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