VFD Controller

www.DataSheet4U.com ePV6200 VFD Controller Version 1.2 ELAN MICROELECTRONICS CORP. No. 12, Innovation 1st RD., Science-Based Industrial Park Hsin Chu City, Taiwan, R.O.C. TEL: (03) 5639977 FAX: (03) 5780617 www.DataSheet4U.com ePV6200 VFD Controller Version History Specification Revision History Version Content ePV6200 1.0 Initial version 1.1 revise error describe Release Date 2004/3/30 2004/04/06 User Application Note (Before using this chip, take a look at the following description note, it includes important messages.) 1. There are some undefined bits in the registers. The values in these bits are unpredicted. These bits are not allowed to use. We use the symbol “-” in the spec to recognize them. 2. You will see some names for the register bits definitions. Some name will be appeared very frequently in the whole spec. The following describes the meaning for the register’s definitions such as bit type, bit name, bit number and so on. RA PAGE0 7 RAB7 R/W-0 Bit type Bit name 6 RAB6 R/W -0 read/write (default value=0) 5 BAB5 R-1 4 RAB4 R/W -1 read/write (default value=1) 3 - 2 RAB2 R read only (w/o default value) 1 RAB1 R-0 0 RAB0 R/W read/write (w/o default value) (undefined) not allowed to use Bit number Register name and its page read only (default value=1) read only (default value=0) This specification is subject to change without further notice. 04/06/2004 (V1.2) 1 www.DataSheet4U.com ePV6200 VFD Controller I. General Description The ePV6200 is an 8 -bit RISC type VFD controller with low power, high speed CMOS technology. This integrated single chip has an on_chip watchdog timer (WDT), one time programming ROM (OTP), data RAM, programmable real time clock/counter, internal interrupt, power down mode, built-in four-wire SPI, IR detector and high voltage output for VFD application. II. Feature CPU ¡EOperating voltage : 2.2V~5.5V at main CLK less then 3.582MHz. Main CLK(Hz):3.582M ~ 17.91M ¡E4k x 13 on chip Program ROM. ¡E256 x 8 on chip data RAM ¡E16 level stack for subroutine nesting ¡E8-bit real time clock/counter (TCC) ¡E8-bit counters : COUNTER1,COUNTER3,COUNTER4,COUNTER5 ¡E16-bit counters : COUNTER2 ¡EOn-chip watchdog timer (WDT) ¡E99.9¢H single instruction cycle commands ¡EFour modes (Main clock can be programmed from 447.829k to 17.91MHz generated by internal PLL) Mode CPU status Main clock 32.768kHz clock status Sleep mode Turn off Turn off Turn off Idle mode Turn off Turn off Turn on Green mode Turn on Turn off Turn on Normal mode Turn on Turn on Turn on ¡E8 level Normal mode frequency : 447.829K , 895.658K , 1.791M , 3.582M , 7.165M , 10.747M , 14.331M , 17.91MHz.. ¡EInput port interrupt function ¡E12 interrupt source , 5 external (IR , INT1~INT4 ), 8 internal( SPI,TCC,COUNTER1~5) ¡EDual clocks operation (Internal PLL main clock , External 32.768KHz) SPI ¡ESerial interface for Clock, Data Input, Data Output, Strobe pins. GPIO ¡EGPIO 9 Port(8 bit) : general purpose input/output; LED output ¡EGPIO C port(8 bit) : general purpose input/output for switch and key scanning(12x4 matrixs) VFD ¡EMany display modes. (9-segment & 19-digit to 20-segment & 8-digit) ¡EMany display modes, can be programmed ¡ENo external resistor necessary for driver outputs.(P-ch open-drain + pull-down resistor output) POR ¡E2.0V Power-on voltage detector reset PACKAGE ¡E52-pin die or 52-pin QFP III. Application DVD-R/W, DVD Recorder, DVD combo VFD Controller This specification is subject to change without further notice. 04/06/2004 (V1.2) 2 www.DataSheet4U.com ePV6200 VFD Controller V. Functional Block Diagram DOUT DIN CLK STB Serial Data Interface MCU 8 GR1… GR8 OSCI OSCO OSC OTP Segment Driver/ Grid Driver/ Data RAM High Breakdown Driver 8 GR9/SG20 … GR16/SG13 GR17/SG12/KS12 … GR19/SG10/KS10 SG9/KS9 … SG5/KS5 SG4/KS4 … SG1/KS1 3 GPIO9[0:7] 8 5 Timer GPIO GPIOC[0:7] 8 4 PLL IR Real Time Clock /RESET PLLC VDDx3 VSS VEE AVDD Fig.2a Block diagram XIN XOUT PLLC WDT Timer Oscillator Timing Control R1(TCC) Interrupt Control Control Sleep And Wakeup On I/O port General RAM Instruction Decoder Instruction Register ALU R3 R5 ROM Prescaler R2 STACK Data RAM R4 Data & Control Bus IOC5 R5 SPI Port5 (HV) IOC6 R6 Port6 (HV) IOC7 R7 Port7 (HV) IOC8 R8 Port8 (HV) IOC9 R9 Port9 IOCC RC PortC P54~P57 P60~P67 P70~P77 P80~P87 P90~P97 PC0~PC7 Fig.2b Block diagram This specification is subject to change without further notice. 04/06/2004 (V1.2) 3 www.DataSheet4U.com ePV6200 VFD Controller Port P54 P55 P56 P57 Port P80 P81 P82 P83 P84 P85 P86 P87 HV SG1/KS1 SG2/KS2 SG3/KS3 SG4/KS4 HV GR8 GR7 GR6 GR5 GR4 GR3 GR2 GR1 Port P60 P61 P62 P63 P64 P65 P66 P67 Port P90 P91 P92 P93 P94 P95 P96 P97 HV SG5/KS5 SG6/KS6 SG7/KS7 SG8/KS8 SG9/KS9 GR19/SG10/KS10 GR18/SG11/KS11 GR17/SG12/KS12 GPIO GPIO90/LED0/IR GPIO91/LED1/INT1 GPIO92/LED2/INT2 GPIO93/LED3/INT3 GPIO94/LED4/INT4 GPIO95/LED5 GPIO96/LED6 GPIO97/LED7 Port P70 P71 P72 P73 P74 P75 P76 P77 Port PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 HV GR16/SG13 GR15 SG14 GR14/SG15 GR13/SG16 GR12/SG17 GR11/SG18 GR10/SG19 GR9/SG20 GPIO GPIOC0/Key1 GPIOC1/Key2 GPIOC2/Key3 GPIOC3/Key4 GPIOC4/STB GPIOC5/CLK GPIOC6/DOUT GPIOC7/ DIN Table.2c Ports Mapping for HV and GPIO This specification is subject to change without further notice. 04/06/2004 (V1.2) 4 www.DataSheet4U.com ePV6200 VFD Controller VII. Functional Descriptions VII.1 Operational Registers Register configuration Addr 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 : 1F 20 : 3F R PAGE0 Indirect addressing TCC PC Page, Status RAM bank, RSR Port5 Output data Port6 Output data Port7 Output data Port8 Output data Port9 I/O data PLL, Main clock,WDTE PortC I/O data Interrupt flag Interrupt flag, Wake-up control Interrupt flag 16 bytes Common registers Bank0~Bank3 Common registers (32x8 for each bank) IOC PAGE registers IOC PAGE1 R PAGE registers R PAGE1 R PAGE2 Program ROM page SPI data buffer Counter1 data Data RAM address Data RAM data buffer Port9 pull high PortC pull high Counter2 LB data Counter2 HB data Counter3 data Counter4 data Counter5 data Addr IOC PAGE0 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F Port9 I/O control Port5 switch Clock source(CN2,CN1) Prescaler(CN2,CN1) Clock source(CN4,CN3) Prescaler(CN4,CN3) Clock source(CN5) Prescaler(CN5) PortC switch PortC I/O control Interrupt mask Interrupt mask Interrupt mask This specification is subject to change without further notice. 04/06/2004 (V1.2) 5 www.DataSheet4U.com ePV6200 VFD Controller VII.2 Operational Register Detail Description R0 (Indirect Addressing Register) R0 is not a physically implemented register. It is used as indirect addressing pointer. Any instruction using R0 as register actually accesses data pointed by the RAM Select Register (R4). Example: Mov A, @0x20 ;store a address at R4 for indirect addressing Mov 0x04, A Mov A, @0xAA ;write data 0xAA to R20 at bank0 through R0 Mov 0x00, A R1 (TCC) TCC data buffer. Increased by 16.384KHz or by the instruction cycle clock (controlled by CONT register). Written and read by the program as any other register. R2 (Program Counter) The structure is depicted in Fig.3. Generates 4k × 13 external ROM addresses to the relative programming instruction codes. "JMP" instruction allows the direct loading of the low 10 program counter bits. "CALL" instruction loads the low 10 bits of the PC, PC+1, and then push into the stack. "RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack. "MOV R2, A" allows the loading of an address from the A register to the PC, and the ninth and tenth bits are cleared to "0''. "ADD R2,A" allows a relative address be added to the current PC, and contents of the ninth and tenth bits are cleared to "0''. Fig.3 Program counter organization R5(PAGE) CALL and INTERRUPT A9 A8 0000 0001 0010 0011 A7~A0 RET RETL RETI STACK1 STACK2 STACK3 STACK4 STACK5 STACK6 STACK7 STACK8 STACK9 STACK10 STACK11 STACK12 STACK13 STACK14 STACK15 STACK16 PC A13 A12 A11 A10 PAGE0 0000~03FF PAGE1 0400~07FF PAGE2 0800~0BFF PAGE3 0C00~0FFF store ACC,R3,R5(PAGE) restore "TBL" allows a relative address added to the current PC, and contents of the ninth and tenth bits don't change. The most significant bit (A10~A13) will be loaded with the contents of bit PS0~PS3 in the status register (R5 PAGE 1) upon the execution of a "JMP'', "CALL'', "ADD R2, A'', or "MOV R2, A'' instruction. If an interrupt is triggered, PROGRAM ROM will jump to address 0x08 at page0. The CPU will store ACC, R3 status and R5 PAGE automatically, and they will be restored after instruction RETI. R3 (Status, Page selection) (Status flag, Page selection bits) 7 6 5 RPAGE1 RPAGE0 IOCPAGE R/W-0 R/W-0 R/W-0 Bit 0(C) : Carry flag Bit 1(DC) : Auxiliary carry flag Bit 2(Z) : Zero flag Bit 3(P) : Power down bit 4 T R 3 P R 2 Z R/W 1 DC R/W 0 C R/W This specification is subject to change without further notice. 04/06/2004 (V1.2) 6 www.DataSheet4U.com ePV6200 VFD Controller Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command. Bit 4(T) : Time-out bit Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT timeout. EVENT WDT wake up from sleep mode WDT time out (not sleep mode) /RESET wake up from sleep Power up Low pulse on /RESET T 0 0 1 1 x P 0 1 0 1 X x : don't care REMARK Bit 5(IOCPAGE) : change IOC5 ~ IOCE to another page 0/1 è IOC page0 / IOC page1 Bit 6, Bit 7(RPAGE0 ~ RPAGE1) : change R5 ~ RC to another page Please refer to VII.1 Operational registers for detail register configuration. (RPAGE1,RPAGE0) (0,0) (0,1) (1,x) R page # selected R page 0 R page 1 R page 2 R4 (RAM selection for common registers R20 ~ R3F)) (RAM selection register) 7 6 5 4 3 2 1 0 RB1 RB0 RSR5 RSR4 RSR3 RSR2 RSR1 RSR0 R/W-0 R/W-0 R/W R/W R/W R/W R/W R/W Bit 0 ~ Bit 5 (RSR0 ~ RSR5) : Indirect addressing for common registers R20 ~ R3F RSR bits are used to select up to 32 regi