N-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET

www.DataSheet4U.com N-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET ISSUE 2 – MARCH 94 FEATURES * 100 Volt VDS * RDS(on)= 4Ω ZVN2110C G D S REFER TO ZVN2110A FOR GRAPHS ABSOLUTE MAXIMUM RATINGS. PARAMETER Drain-Source Voltage Continuous Drain Current at Tamb=25°C Pulsed Drain Current Gate Source Voltage Power Dissipation at Tamb=25°C Operating and Storage Temperature Range SYMBOL VDS ID IDM VGS Ptot Tj:Tstg E-Line TO92 Compatible VALUE 100 320 6 ± 20 UNIT V mA A V mW °C 700 -55 to +150 ELECTRICAL CHARACTERISTICS (at Tamb = 25°C unless otherwise stated). PARAMETER Drain-Source Breakdown Voltage Gate-Source Threshold Voltage Gate-Body Leakage Zero Gate Voltage Drain Current On-State Drain Current(1) Static Drain-Source On-State Resistance (1) Forward Transconductance (1)(2) Input Capacitance (2) Common Source Output Capacitance (2) Reverse Transfer Capacitance (2) Turn-On Delay Time (2)(3) Rise Time (2)(3) Turn-Off Delay Time (2)(3) Fall Time (2)(3) SYMBOL MIN. BVDSS VGS(th) IGSS IDSS ID(on) RDS(on) gfs Ciss Coss Crss td(on) tr td(off) tf 250 75 25 8 7 8 13 13 1.5 4 100 0.8 2.4 20 1 100 MAX. UNIT CONDITIONS. V V nA µA µA ID=1mA, VGS=0V ID=1mA, VDS= VGS VGS=± 20V, VDS=0V VDS=100V, VGS=0 VDS=80V, VGS=0V, T=125°C(2) VDS=25V, VGS=10V VGS=10V,ID=1A VDS=25V,ID=1A A Ω mS pF pF pF ns ns ns ns VDS=25 V, VGS=0V, f=1MHz VDD ≈25V, ID=1A (1) Measured under pulsed conditions. Width=300µs. Duty cycle ≤2% (2) Sample test. 3-367 ( 3 )