32 Channel Voice Echo Canceller

www.DataSheet4U.com ZL38065 32 Channel Voice Echo Canceller Data Sheet Features • Independent multiple channels of echo cancellation; from 32 channels of 64 ms to 16 channels of 128 ms with the ability to mix channels at 128 ms or 64 ms in any combination Fully compliant to ITU-T G.165, G.168 (2000) and (2002) specifications Passed all AT&T voice quality tests for carrier grade echo canceller systems. Unparalleled in-system tunability Sub 50 ms initial convergence times under many typical network conditions Fast reconvergence on echo path changes Patented Advanced Non-Linear Processor with high quality subjective performance Superior noise matching algorithm PCM coding, µ/A-Law ITU-T G.711 or sign magnitude Per channel Fax/Modem G.164 2100 Hz or G.165 2100 Hz phase reversal Tone Disable Per channel echo canceller parameters control Transparent data transfer and mute Protection against narrow band signal divergence and instability in high echo environments • • • • • • Ordering Information ZL38065QCG ZL38065GDG ZL38065QCG1 ZL38065GDG2 100 208 100 208 Pin LQFP Ball LBGA Pin LQFP* Ball LBGA** Trays, Trays, Trays, Trays, Bake Bake Bake Bake & & & & Drypack Drypack Drypack Drypack January 2006 • • • • • • • • • • • • *Pb Free Matte Tin **Pb Free Tin/Silver/Copper -40°C to +85°C +9 dB to -12 dB level adjusters (3 dB steps) at all signal ports Offset nulling of all PCM channels Independent Power Down mode for each group of 2 channels for power management Compatible to ST-BUS and GCI interface at 2 Mbps serial PCM 3.3 V pads and 1.8 V Logic core operation with 5 V tolerant inputs IEEE-1149.1 (JTAG) Test Access Port Applications • • • Voice over IP network gateways Voice over ATM, Frame Relay T1/E1/J1 multichannel echo cancellation VDD1 (3.3V) VSS VDD2 (1.8 V) ODE Echo Canceller Pool Rin Sin MCLK Fsel PLL Serial to Parallel Group 0 ECA/ECB Group 1 ECA/ECB Group 2 ECA/ECB Group 3 ECA/ECB Parallel to Serial Rout Sout Group 4 ECA/ECB Group 5 ECA/ECB Group 6 ECA/ECB Group 7 ECA/ECB Group 8 ECA/ECB Group 9 ECA/ECB Group 10 ECA/ECB Group 11 ECA/ECB Group 12 ECA/ECB C4i F0i Timing Unit Group 13 ECA/ECB Group 14 ECA/ECB Group 15 ECA/ECB Note: Refer to Figure 4 for Echo Canceller block diagram IC0 RESET Microprocessor Interface Test Port DS CS R/W A12-A0 DTA D7-D0 IRQ TMS TDI TDO TCK TRST Figure 1 - ZL38065 Device Overview 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved. ZL38065 • • Wireless base stations Echo Canceller pools Data Sheet Description The ZL38065 Voice Echo Canceller implements a cost effective solution for telephony voice-band echo cancellation conforming to ITU-T G.168 requirements. The ZL38065 architecture contains 16 groups of two echo cancellers (ECA and ECB) which can be configured to provide two channels of 64 ms or one channel of 128 ms echo cancellation. This provides 32 channels of 64 ms to 16 channels of 128 ms echo cancellation or any combination of the two configurations. The ZL38065 supports ITU-T G.165 and G.164 tone disable requirements. PLLVSS1 PLLVSS2 PLLVDD VDD1 VDD2 Mclk NC IC0 IC0 IC0 IC0 IC0 VDD1 77 VSS fsel NC NC NC NC NC VSS NC NC NC 78 TMS TDI TDO TCK VSS TRSTB IC0 RESETB IRQB DS CS R/W DTA NC 76 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 99 98 97 96 95 94 93 (100 pin LQFP) 92 ZL38065QC 91 90 89 88 87 86 85 84 83 82 81 80 79 NC NC NC IC0 IC0 IC0 VSS IC0 IC0 IC0 IC0 VDD2 C4ib Foib Rin Sin Rout Sout ODE VSS NC NC NC NC NC 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 VDD2 D0 D1 D2 VSS D3 D4 D5 D6 D7 NC NC VDD1 = 3.3 V VDD2 = 1.8 V 51 30 31 50 A12 VSS A11 VSS NC NC NC VDD1 VDD2 A10 NC VDD1 NC A6 Figure 2 - 100 Pin LQFP 2 Zarlink Semiconductor Inc. NC NC A0 A1 A2 A3 A4 A5 A7 A8 A9 26 27 28 29 32 33 34 35 36 37 38 39 41 40 42 43 45 44 46 47 48 49 ZL38065 Table of Contents Data Sheet 1.0 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1 Adaptive Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 Double-Talk Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3 Path Change Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.4 Non-Linear Processor (NLP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.5 Disable Tone Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.6 Instability Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.7 Narrow Band Signal Detector (NBSD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.8 Offset Null Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.9 Adjustable Level Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.10 ITU-T G.168 Compliance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.0 Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 Normal Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 Back-to-Back Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3 Extended Delay Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.0 Echo Canceller Functional States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 Mute. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 Disable Adaptation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 Enable Adaptation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.0 ZL38065 Throughput Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.0 Serial PCM I/O channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 Serial Data Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.0 Memory Mapped Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 Normal Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2 Extended Delay Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3 Back-to-Back Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.4 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.5 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.6 Call Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.0 JTAG Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.1 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.3 Test Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3 Zarlink Semiconductor Inc. ZL38065 List of Figures Data Sheet Figure 1 - ZL38065 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - 100 Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .