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ZL38010 Low Power Quad ADPCM Transcoder
Data Sheet Features
• • Full duplex transcoder with four encode channels and four decode channels 32 kbps, 24 kbps and 16 kbps ADPCM coding complying with ITU-T (previously CCITT) G.726 (without 40 kbps), and ANSI T1.303-1989 Low power operation, 6.5 mW typical Asynchronous 4.096 MHz master clock operation SSI and ST-BUS interface options Transparent PCM bypass Transparent ADPCM bypass Linear PCM code No microprocessor control required Simple interface to Codec devices Pin selectable µ−Law or A-Law operation Pin selectable ITU-T or signed magnitude PCM coding Single 3.3 Volts power supply Ordering Information ZL38010DCE 28 Pin SOIC ZL38010DCF 28 Pin SOIC ZL38010DCE1 28 Pin SOIC** ZL38010DCF1 28 Pin SOIC** **Pb Free Matte Tin -40°C to +85°C Tubes Tape & Reel Tubes Tape & Reel
January 2007
• • • • • • • • • • •
Applications
• • • Pair gain Voice mail systems Wireless telephony systems
Description
The Quad ADPCM Transcoder is a low power, CMOS device capable of four encode and four decode functions per frame. Four 64 kbps PCM octets are compressed into four 32, 24 or 16 kbps ADPCM words, and four 32, 24 or 16 kbps ADPCM words are expanded into four 64 kbps PCM octets. The 32, 24 and 16 kbps ADPCM transcoding algorithms utilized conform to ITU-T Recommendation G.726 (excluding 40 kbps), and ANSI T1.303 - 1989.
ADPCMi ADPCMo
ADPCM I/O
Full Duplex Quad Transcoder
PCM I/O
PCMo1 PCMi1
PCMo2 PCMi2
ENB1 ENB2/F0od BCLK F0i MCLK C2o EN1 EN2 Timing Control Decode
VDD VSS PWRDN IC
MS1 MS2 MS3 A/µ FORMAT MS4 MS5 MS6 LINEAR SEL
Figure 1 - Functional Block Diagram 1
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2005-2007, Zarlink Semiconductor Inc. All Rights Reserved.
ZL38010
Data Sheet
Switching, on-the-fly, between 32 kbps and 24 kbps ADPCM, is possible by controlling the appropriate mode select (MS1 - MS6) control pins. All optional functions of the device are pin selectable allowing a simple interface to industry standard codecs, digital phone devices and Layer 1 transceivers. Linear coded PCM is provided to facilitate external DSP functions.
Change Summary
Changes from October 2005 Issue to January 2007 Issue. Page 1 Item Ordering Information Box Change Added Pb Free part numbers.
EN1 MCLK F0i C2o BCLK PCMo1 PCMi1 VSS LINEAR ENB2/F0od ENB1 PCMo2 PCMi2 SEL
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
EN2 MS6 MS5 MS4 ADPCMo ADPCMi VDD MS3 MS2 MS1 IC PWRDN FORMAT A/µ
Figure 2 - Pin Connections Pin Description Pin # 1 Name EN1 Description Enable Strobe 1 (Output). This 8 bit wide, active high strobe is active during the B1 PCM channel in ST-BUS mode. Becomes a single bit, high true pulse when LINEAR=1. In SSI mode this output is high impedance. Master Clock (input). This is a 4.096 MHz (minimum) input clock utilized by the transcoder function; it must be supplied in both ST-BUS and SSI modes of operation. In ST-BUS mode the C4 ST-BUS clock is applied to this pin. This synchronous clock is also used to control the data I/O flow on the PCM and ADPCM input/output pins according to ST-BUS requirements. In SSI mode this master clock input is derived from an external source and may be asynchronous with respect to the 8 kHz frame. MCLK rates greater than 4.096 MHz are acceptable in this mode since the data I/O rate is governed by BCLK. 3 4 F0i C2o Frame Pulse (Input). Frame synchronization pulse input for ST-BUS operation. SSI operation is enabled by connecting this pin to VSS. 2.048 MHz Clock (Output). This ST-BUS mode bit clock output is the MCLK (C4) input divided by two, inverted, and synchronized to F0i. This output is high-impedance during SSI operation.
2
MCLK
2
Zarlink Semiconductor Inc.
ZL38010
Pin # 5 Name BCLK Description
Data Sheet
Bit Clock (Input). 128 kHz to 4096 kHz bit clock input for both PCM and ADPCM ports; used in SSI mode only. The falling edge of this clock latches data into ADPCMi, PCMi1 and PCMi2. The rising edge clocks data out on ADPCMo, PCMo1 and PCMo2. This input must be tied to VSS for ST-BUS operation. Serial PCM Stream 1 (Output). 128 kbps to 4096 kbps serial companded/linear PCM output stream. Data are clocked out by rising edge of BCLK in SSI mode. Clocked out by MCLK divided by two in ST-BUS mode. See Figure 14. Serial PCM Stream 1 (Input). 128 kbps to 4096 kbps serial companded/linear PCM input stream. Data are clocked in on falling edge of BCLK in SSI mode. Clocked in at the 3/4 bit position of MCLK in ST-BUS mode. See Figure 14. Digital Ground. Nominally 0 volts Linear PCM Select (Input). When tied to VDD the PCM I/O ports (PCM1,PCM2) are 16bit linear PCM. Linear PCM operates only at a bit rate of 2048 kbps. Companded PCM is selected when this pin is tied to VSS. See Figure 5 & Figure 8. PCM B-Channel Enable Strobe 2 (Input) / Delayed Frame Pulse (Output). SSI operation: ENB2 (Input). An 8-bit wide enable strobe input defining B2 channel (AD)PCM data. A valid 8-bit strobe must be present at this input for SSI operation. See Figure 4 & Figure 6. ST-BUS operation: F0od (Output). This pin is a delayed frame strobe output. When LINEAR=0, this becomes a delayed frame pulse output occurring 64 C4 clock cycles after F0i and when LINEAR = 1 at 128 C4 clock cycles after F0i. See Figures 7, 8, 9 & 14.
6
PCMo1
7
PCMi1
8 9
VSS LINEAR
10
ENB2/F0od
11
ENB1
PCM B-Channel Enable Strobe 1 (Input). SSI operation: An 8-bit wide enable strobe input defining B1 channel (AD)PCM data. A valid 8-bit strobe must be present at this input for SSI operation. ST-BUS operation: When tied to VSS transparent bypass of the ST-BUS D- and C- channels is enabled. When tied to VDD the ST-BUS D-channel and C-channel output timeslots are forced to a high-impedance state.
12
PCMo2
Serial PCM Stream 2 (Output). 128 kbps to 4096 kbps serial companded/linear PCM output stream. Clocked out by rising edge of BCLK in SSI mode. Clocked out by MCLK divided by two in ST-BUS mode. See Figure 14. Serial PCM Stream 2 (Input). 128 kbps to 4096 kbps serial companded/linear PCM input stream. Data bits are clocked in on falling edge of BCLK in SSI mode. Clocked in at the 3/4 bit position of MCLK in ST-BUS mode. See Figure 14. SELECT (Input). PCM bypass mode: When SEL=0 the PCM1 port is selected for PCM bypass operation and when SEL=1 the PCM2 port is selected for PCM bypass operation. See Figure 6 & Figure 9. 16 kbps transcoding mode: SSI Operation - in 16 kbps transcoding mode, the ADPCM words are assigned to the I/O timeslot defined by ENB2 when SEL=1 and by ENB1 when SEL=0. See Figure 4. ST-BUS operation- in 16 kbps transcoding mode, the ADPCM words are assigned to the B2 timeslot when SEL=1 and to the B1 timeslot when SEL=0. See Figure 9.
13
PCMi2
14
SEL
3
Zarlink Semiconductor Inc.
ZL38010
Pin # 15 Name A/µ Description
Data Sheet
A-Law/µ−Law Select (Input). This input pin selects µ−Law companding when set to logic 0, and A-Law companding when set to logic 1. This control is for all channels.This input is ignored in Linear mode during which it may be tied to VSS or VDD. FORMAT Select (Input). Selects ITU-T PCM coding when high and Sign-Magnitude PCM coding when low. This control is for all channels.This input is ignored in Linear mode during which it may be tied to VSS or VDD. Power-down (Input). An active low reset forcing the device into a low power mode where all outputs are high-impedance and device operation is halted. Internal Connection (Input). Tie to VSS for normal operation. Mode Selects 1, 2 and 3 (Inputs). Mode selects for all four encoders. MODE MS3 MS2 MS1 0 0 0 32 kbps ADPCM 0 0 1 24 kbps ADPCM 0 1 0 16 kbps ADPCM in EN1/ENB1 when SEL=0 in EN2/ENB2 when SEL=1 0 1 1 ADPCM Bypass for 32 kbps and 24 kbps 1 0 0 ADPCM Bypass for 16 kbps 1 0 1 PCM Bypass (64 kbps) to PCM1 if SEL=0, PCM2 if SEL=1 1 1 0 Algorithm reset (ITU-T optional reset) 1 1 1 ADPCMo disable Positive Power Supply. Nominally 3.3 Volts +/-10% Serial ADPCM Stream (Input). 128 kbps to 4096 kbps serial ADPCM word input stream. Data bits are clocked in on falling edge of BCLK in SSI mode and clocked in on the 3/4 bit edge of MCLK in ST-BUS mode. Serial ADPCM Stream (Output). 128 kbps to 4096 kbps serial ADPCM word output stream. Data bits are clocked out by rising edge of BCLK in SSI mode and clocked out by MCLK divided by two in ST-BUS mode. Mode Selects 4, 5 and 6 (Inputs). Mode selects for all four decoders. MODE MS6 MS5 MS4 0 0 0 32 kbps ADPCM 0 0 1 24 kbps ADPCM 0 1 0 16 kbps ADPCM in EN1/ENB1 when SEL=0 in EN2/ENB2 when SEL=1 0 1 1 ADPCM Bypass for 32 kbps and 24 kbps 1 0 0 ADPCM Bypass for 16 kbps 1 0 1 PCM Bypass (64 kbps) to PCM1 if SEL=0, PCM2 if SEL=1 1 1 0 Algorithm reset (ITU-T optional reset) 1 1 1 PCMo1/2 disable Enable Strobe 2 (Output). This 8 bit wide, active high strobe is active during the B2 PCM channel in ST-BUS mode. Forced to high impedance when LINEAR=1.
16
FORMAT
17 18 19 20 21
PWRDN IC MS1 MS2 MS3
22 23
VDD ADPCMi
24
ADPCMo
25 26 27
MS4 MS5 MS6
28
EN2
Note: All unused inputs should be connected to logic low or high unless otherwise stated. All outputs should be left open circuit when not used. All inputs have TTL compatible logic levels except for MCLK which has CMOS compatible logic levels and PWRDN which has Schmitt trigger compatible logic levels. All outputs are CMOS with CMOS logic levels (See DC Electrical Characteristics).
4
Zarlink Semiconductor Inc.
ZL38010
Functional Description
Data Sheet
The Quad-channel ADPCM Transcoder is a low power, CMOS device capable of four encode and four decode operations per frame. Four 64 kbps channels (PCM octets) are compressed into four 32, 24 or 16 kbps ADPCM channels (ADPCM words), and four 32, 24 or 16 kbps ADPCM channels (ADPCM words) are expanded into four 64 kbps PCM channels (PCM octets). The ADPCM transcoding algor
