Digital Echo Canceller

www.DataSheet4U.com ZL38002 Digital Echo Canceller for Hands Free Communication Data Sheet Features • • • • • • • • • • • • • • 112 ms acoustic echo canceller Up to 12 dB of noise reduction Works with low cost voice codec. ITU-T G.711 or signed mag µ/A-Law, or linear 2’s compliment Each port may operate independently in companded format or linear format Advanced NLP design - full duplex speech with no switched loss on audio paths Fast re-convergence time: tracks changing echo environment quickly Adaptation algorithm converges even during Double-Talk Designed for exceptional performance in high background noise environments Provides protection against narrow-band signal divergence Howling prevention stops uncontrolled oscillation in high loop gain conditions Programmable offset nulling of all PCM channels Serial micro-controller interface Idle channel noise suppression ST-BUS, GCI, or variable-rate SSI PCM interfaces Limiter ADV NLP January 2007 Ordering Information ZL38002QDG ZL38002QDG1 ZL38002DGE1 ZL38002DGF1 48 48 36 36 TQFP Trays TQFP* Trays QSOP* Tubes, Bake & Drypack QSOP* Tape & Reel, Bake & Drypack *Pb Free Matte Tin -40°C to 85°C Pin Pin Pin Pin • • • • • • • • • User gain control provided for speaker path (-24 dB to +21 dB in 3 dB steps) Adjustable gain pads from -24 dB to +21 dB at Xin, Sin and Sout to compensate for different system requirements AGC on speaker path Handles up to -6 dB acoustic echo return loss (with the appropriate gain pad settings) Transparent data transfer and mute options 20 MHz master clock operation Low power mode during PCM Bypass Bootloadable for future factory software upgrades 2.7 V to 3.6 V supply voltage; 5 V-tolerant inputs Sin MD1 µ/A-Law/ Linear HP Filter Gain Pad S1 + + - S2 Noise Reduction Gain Pad Program RAM Linear/ µ/A-Law Sout DATA1 DATA2 ACOUSTIC ECHO PATH NBSD Adaptive Filter CONTROL UNIT Double Talk Detector R1 R1 NBSD Program ROM Micro Interface Gain Pad Howling Controller SCLK MD2 Rout Linear/ µ/A-Law Limiter -24 -> +21dB CS HP Filter µ/A-Law/ Linear AGC User Gain Rin VDD VSS RESET FORMAT ENA2 ENA1 LAW F0i BCLK/C4i MCLK Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2005-2007, Zarlink Semiconductor Inc. All Rights Reserved. ZL38002 Applications • • • • • Hands free car kits Full duplex speaker-phone for digital telephone Echo cancellation for video conferencing Security systems Intercom systems (door entry, elevator, and restaurant drive-through) Data Sheet MT93L16 Description AEC for analog handsfree communication Application Analog Desktop phone Analog Intercom Features AEC LEC Gains Noise Reduction Integrated Codecs 1 channel 1 channel User Gain N N ZL38001 ZL38002 ZL38003 AEC with noise reduction & codecs for digital hands-free communication AEC for analog hands- AEC with noise reduction for digital free communication hands-free communication Analog Desktop phone Hands-free Car Kits Hands-free Car Kits Analog Intercom Digital Desktop Phone Home Security Digital Desktop Phone Home Security Intercom & Pedestals Intercom & Pedestals 1 channel 1 channel User Gain/18 dB Gain on Sout N N 1 channel Custom Load User Gain + System tuning gains Y N 1 channel Custom Load User Gain + System tuning gains Y dual channel Table 1 - Acoustic Echo Cancellation Family 2 Zarlink Semiconductor Inc. ZL38002 Data Sheet MCLK Figure 2 - Pin Connections Pin Description QSOP Pin # 1 TQFP Pin # 43 Name ENA1 Description SSI Enable Strobe/ST-BUS & GCI Mode for Rin/Sout (Input). This pin has dual functions depending on whether SSI or ST-BUS/GCI is selected. For SSI, this strobe must be present for frame synchronization. This is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial PCM data transfer for on Rin/Sout pins. Strobe period is 125 ms. For STBUS or GCI, this pin, in conjunction with the MD1 pin, selects the proper mode for Rin/Sout pins (see ST-BUS and GCI Operation description). ST-BUS & GCI Mode for Rin/Sout (Input). When in ST-BUS or GCI operation, this pin, in conjunction with the ENA1 pin, will select the proper mode for Rin/Sout pins (see ST-BUS and GCI Operation description). Connect this pin to Vss in SSI mode. SSI Enable Strobe /ST-BUS & GCI Mode for Sin/Rout (Input). This pin has dual functions depending on whether SSI or ST-BUS/GCI is selected. For SSI, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial PCM data transfer on Sin/Rout pins. Strobe period is 125 ms. For ST-BUS/GCI, this pin, in conjunction with the MD2 pin, selects the proper mode for Sin/Rout pins (see ST-BUS and GCI Operation description). ST-BUS & GCI Mode for Sin/Rout (Input). When in ST-BUS or GCI operation, this pin in conjunction with the ENA2 pin, selects the proper mode for Sin/Rout pins (see ST-BUS and GCI Operation description). Connect this pin to Vss in SSI mode. 2 45 MD1 3 46 ENA2 4 47 MD2 3 Zarlink Semiconductor Inc. IC IC IC LAW NC FORMAT NC ENA1 MD1 ENA2 MD2 Rin Sin IC MCLK IC IC IC LAW FORMAT RESET NC NC SCLK CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 QSOP 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 IC IC IC MCLK2 NC VSS VDD2 VSS2 IC IC BCLK/C4i F0i Rout Sout VDD NC DATA1 DATA2 NC MCLK2 IC IC IC NC ENA1 NC MD1 ENA2 MD2 Rin 36 38 40 NC VSS VDD2 VSS2 NC IC IC BCLK/C4i NC F0i Rout NC 34 32 30 28 26 24 22 20 42 44 16 46 14 48 2 4 6 8 10 12 TQFP 18 Sout VDD NC DATA1 NC DATA2 NC CS SCLK NC NC RESETB NC Sin IC NC ZL38002 Pin Description (continued) QSOP Pin # 5 TQFP Pin # 48 Name Rin Description Data Sheet Receive PCM Signal Input (Input). 128 kbps to 4096 kbps serial PCM input stream. Data may be in either companded or 2’s complement linear format. This is the Receive Input channel from the line (or network) side. Data bits are clocked in following SSI, GCI or ST-BUS timing requirements. Send PCM Signal Input (Input). 128 kbps to 4096 kbps serial PCM input stream. Data may be in either companded or 2’s complement linear format. This is the Send Input channel (from the microphone). Data bits are clocked in following SSI, GCI or ST-BUS timing requirements. Internal Connection (Input). Must be tied to Vss. Master Clock (Input). Nominal 20 MHz Master Clock input (can be asynchronous relative to 8 KHz frame signal.) Tie together with MCLK2. Internal Connection (Input). Must be tied to Vss. A/µ Law Select (Input). When low, selects µ−Law companded PCM. When high, selects A-Law companded PCM. This control is for both serial pcm ports. 6 2 Sin 7 8 9,10,11 12 3 5 6, 7, 8 9 IC MCLK IC LAW 13 11 FORMAT ITU-T/Sign Mag (Input). When low, selects sign-magnitude PCM code. When high, selects ITU-T (G.711) PCM code. This control is for both serial pcm ports. RESET SCLK CS DATA2 Reset / Power-down (Input). An active low resets the device and puts the ZL38002 into a low-power stand-by mode. Serial Port Synchronous Clock (Input). Data clock for the serial microport interface. Serial Port Chip Select (Input). Enables serial microport interface data transfers. Active low. Serial Data Receive (Input). In Motorola/National serial microport operation, the DATA2 pin is used for receiving data. In Intel serial microport operation, the DATA2 pin is not used and must be tied to Vss or Vdd. Serial Data Port (Bidirectional). In Motorola/National serial microport operation, the DATA1 pin is used for transmitting data. In Intel serial microport operation, the DATA1 pin is used for transmitting and receiving data. Positive Power Supply (Input). Nominally 3.3 volts. Send PCM Signal Output (Output). 128 kbps to 4096 kbps serial PCM output stream. Data may be in either companded or 2’s complement linear PCM format. This is the Send Out signal after acoustic echo cancellation and non-linear processing. Data bits are clocked out following SSI, STBUS or GCI timing requirements. Receive PCM Signal Output (Output). 128 kbps to 4096 kbps serial PCM output stream. Data may be in either companded or 2’s complement linear PCM format. This is the Receive out signal after the AGC and gain control. Data bits are clocked out following SSI, ST-BUS or GCI timing requirements. 14 17 18 19 13 16 17 19 20 21 DATA1 22 23 23 24 VDD Sout 24 26 Rout 4 Zarlink Semiconductor Inc. ZL38002 Pin Description (continued) QSOP Pin # 25 TQFP Pin # 27 Name F0i Description Data Sheet Frame Pulse (Input). In ST-BUS (or GCI) operation, this is an active-low (or active-high) frame alignment pulse, respectively. SSI operation is enabled by connecting this pin to Vss. 26 29 BCLK/C4i Bit Clock/ST-BUS Clock (Input). In SSI operation, BCLK pin is a 128 kHz to 4.096 MHz bit clock. This clock must be synchronous with ENA1 and ENA2 enable strobes. In ST-BUS or GCI operation, C4i pin must be connected to the 4.096 MHz (C4) system clock. IC VSS2 VDD2 VSS MCLK2 IC NC Internal Connection (Input). Tie to Vss. Digital Ground (Input). Nominally 0 volts. Positive Power Supply (Input). Nominally 3.3 volts (tie together with VDD). Digital Ground (Input). Nominally 0 volts (tie together with VSS2). Master Clock (Input). Nominal 20 MHz master clock (tie together with MCLK). Internal Connection (Input). Tie to Vss. No Connect (Output). This pin should be left unconnected. 27, 28 29 30 31 33 34,35,36 15, 16, 21, 32 30, 31 33 34 35 38 39, 40, 41 1, 4, 10, 12, 14, 15, 18, 20, 22, 25, 28, 32, 36, 37, 42, 44 5 Zarlink Semiconductor Inc. ZL38002 Table of Contents Data Sheet 1.0 Changes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 Noise Reduct