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Zilog
Zilog

Z380 Datasheet

Microprocessor


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ZILOG
PRODUCT SPECIFICATION
MICROPROCESSOR
FEATURES
s Static CMOS Design with Low-Power Standby Mode
Option
s 32-Bit Internal Data Paths and ALU
s Operating Frequency
- DC-to-18 MHz at 5V
- DC-to-10 MHz at 3.3V
s Enhanced Instruction Set that Maintains Object-Code
Compatibility with Z80® and Z180Microprocessors
s 16-Bit (64K) or 32-Bit (4G) Linear Address Space
s 16-Bit Data Bus with Dynamic Sizing
Z380
MICROPROCESSOR
s Two-Clock Cycle Instruction Execution Minimum
s Four Banks of On-Chip Register Files
s Enhanced Interrupt Capabilities, Including
16-Bit Vector
s Undefined Opcode Trap for Z380Instruction Set
s On-Chip I/O Functions:
- Six-Memory Chip Selects with Programmable Waits
- Programmable I/O Waits
- DRAM Refresh Controller
s 100-Pin QFP Package
GENERAL DESCRIPTION
The Z380Microprocessor is an integrated high-
performance microprocessor with fast andefficientthrough-
put and increased memory addressing capabilities. The
Z380offers a continuing growth path for present Z80-or
Z180-based designs, while maintaining Z80® CPU and
Z180® MPU object-code compatibility. The Z380MPU
enhancements include an improved 280 CPU, expanded
4-Gbyte space and flexible bus interface timing.
An enhanced version of the Z80 CPU is key to the Z380
MPU. The basic addressing modes of the Z80 micropro-
cessor have been augmented as follows: Stack Pointer
Relative loads and stores, 16-bit and 24-bit indexed off-
sets, and more flexible Indirect Register addressing, with
all of the addressing modes allowing access to the entire
32-bit address space. Additions made to the instruction
set, include a full complement of 16-bit arithmetic and
logical operations, 16-bit I/O operations, multiply and
divide, plus a complete set of register-to-register loads
and exchanges.
The expanded basic register file of the Z80 MPU micropro-
cessor includes alternate register versions of the IX and IY
registers. There are four sets of this basic Z80 micropro-
cessor register file present in the Z380 MPU, along with the
necessary resources to manage switching between the
different register sets. All of the register-pairs and index
registers in the basic Z80 microprocessor register file are
expanded to 32 bits.
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PS010001-0301
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ZILOG
MICROPROCESSOR
GENERAL DESCRIPTION (Continued)
The Z380 MPU expands the basic 64 Kbyte Z80 and Z180
address space to a full 4 Gbyte (32-bit) address space.
This address space is linear and completely accessible to
the user program. The I/O address space is similarly
expanded to a full 4 Gbyte (32-bit) range and 16-bit I/O,
and both simple and block move are added.
Some features that have traditionally been handled by
external peripheral devices have been incorporated in the
design of the Z380 microprocessor. The on-chip peripher-
als reduce system chip count and reduce interconnection
on the external bus. The Z380 MPU contains a refresh
controller for DRAMs that employs a /CAS-before-/RAS
refresh cycle at a programmable rate and burst size.
Six programmable memory-chip selects are available,
along with programmable wait-state generators for each
chip-select address range.
The Z380 MPU provides flexible bus interface timing, with
separate control signals and timing for memory and
I/O. The memory bus control signals provide timing refer-
ences suitable for direct interface to DRAM, static RAM,
EPROM, or ROM. Full control of the memory bus timing is
possible because the /WAIT signal is sampled three times
during a memory transaction, allowing complete user
control of edge-to-edge timing between the reference
signals provided by the Z380 MPU. The I/O bus control
signals allow direct interface to members of the Z80 family
of peripherals, the Z8000 family of peripherals, or the
Z8500 series of peripherals. Figure 1 shows the Z380
block diagram; Figure 2 shows the pin assignments.
Note:
All signals with a preceding front slash, "/", are active Low
e.g., B//W (WORD is active Low); B/W is active Low, only)
Power connections follow conventional descriptions below:
Connection
Circuit
Device
Power
Ground
VCC
GND
VDD
VSS
Clock with
Standby
Control
Chip Selects
and Waits
Refresh
Control
External Interface Logic
CPU
Data (16)
Address (32)
Interrupts
www.DataSheet4U.com Figure 1. Z380 Functional Block Diagram
/EV
VDD
VSS
PS010001-0301
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ZILOG
MICROPROCESSOR
A5
A4
A3
A2
A1
A0
VSS
VDD
VSS
VDD
/TREFR
/TREFA
/TREFC
/BHEN
/BLEN
/MRD
/MWR
/MSIZE
/WAIT
BUSCLK
IOCLK
/M1
/IORQ
/IORD
CLKI
CLKO
/IOWR
VSS
VDD
VSS
100
1
95
90
85 80
2
5
75
10
Z380
15 100-Pin QFP
70
65
20
60
25
55
30 35 40 45 50
A23
A24
A25
A26
A27
A28
A29
A30
A31
VSS
VDD
VSS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
VDD
VSS
Figure 2. 100-Pin QFP Pin Assignments
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PS010001-0301
Page 3
Part Number Z380
Manufactur Zilog
Description Microprocessor
Total Page 70 Pages
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