SONET/SDH OC-12 TO 12XDS3/E3 MAPPER

www.DataSheet4U.com NOVEMBER 2006 XRT94L43 SONET/SDH OC-12 TO 12XDS3/E3 MAPPER REV. 1.0.2 GENERAL DESCRIPTION The XRT94L43 is an SDH to PDH physical layer processor with integrated SONET OC-12 and 12 DS3/E3 framing controller. The XRT94L43 contains an integral SONET framer which provides framing and error accumulation in accordance with ANSI/ITUT specifications. For a multiple channel DS3/E3 feature, each channel contains identical elements. The configuration of this device is through internal registers accessible via an 8-bit parallel, memory mapped, microprocessor interface. The SONET/SDH transmit and receive blocks are used to transmit/receive an STS-12/STM-4 signals or compose and decompose 12, STS-1/DS3/E3 signals. The blocks operate at a peak internal clock speed of 77 MHz and support 8-bit internal data paths. The transmit and receive blocks are compliant with both SONET and SDH standards. The XRT94L43 performs all SONET transport and path overhead processing for use in broadband data transport applications. FEATURES • Single Chip solution for 12 DS3/E3 to SONET/SDH Mapping • Generates and terminates SONET section, line and path layers. • Provides SONET descrambling. frame scrambling and • Differential Line Interfaces • 8-bit microprocessor interface • Requires +2.5 and +3.3V power supplies with +5V input tolerance • -40°C to +85°C Operating Temperature Range • Available in a 516 Ball PBGA package APPLICATIONS • Network switches • Concentrators • Frame Relay Switches • SONET Customer Premises Multiplexers • Network Access Equipment • Test/Monitoring Equipment Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com XRT94L43 REV. 1.0.2 SONET/SDH OC-12 TO 12XDS3/E3 MAPPER FIGURE 1. BLOCK DIAGRAM OF THE XRT94L43 WHEN CONFIGURED IN SONET MODE Tx STM -4 Tx STM -4 SOH Processor SOH Processor Block Block Tx AU -4 Tx AU -4 Mapper/VC -4 Mapper/VC -4 POH POH Processor Processor Block Block Tx TUG -3 Tx TUG -3 Mapper / Mapper / VC -Tx POH-3 3 VC -Tx VC -3 3 POH VC Processor POH Processor POH Block Processor Block Processor Block Block DS3/E3 DS3/E3 Jitter Jitter Attenuator Attenuator Block Block Rx STM - 4 SOH Rx STM - 4 SOH Processor Processor Block Block STM -4 STM -4 Telecom Bus Telecom Bus Block Block SERDES SERDES Block Block (Primary) (Primary) SERDES SERDES Block Block (APS) (APS) DS3/E3 DS3/E3 DS3/E3 DS3/E3 Mapper DS3/E3 Mapper DS3/E3 Mapper Mapper Block Mapper Block Mapper Block Block Block Block Rx AU -4 Rx AU -4 Mapper/VC -4 Mapper/VC -4 POH POH Processor Processor Block Block AUG # 1 To AUG # 2 From AUG # 2 Clock Synthesizer Block Clock Synthesizer Block - 4 - 4 Rx TUG -3 Rx TUG -3 Mapper / Mapper / VC - 3 POH VC - 3 POH Processor Processor Block Block DS3/E3 DS3/E3 DS3/E3 Framer DS3/E3 DS3/E3 Framer Framer DS3/E3 Block Framer Framer Block Block Framer Block Block Block Microprocessor Interface Microprocessor Interface JTAG Test Port JTAG Test Port 2 XRT94L43 SONET/SDH OC-12 TO 12XDS3/E3 MAPPER FIGURE 2. BLOCK DIAGRAM OF THE XRT94L43 WHEN CONFIGURED IN SDH/TUG-3 MODE REV. 1.0.2 TxS -4 TM TxS -4 TM S HP O rocessor S HP O rocessor B lock B lock Tx A -3 U Tx A -3 U M apper/V -3 C M apper/V -3 C P H O P H O P rocessor P rocessor B lock B lock R V -3 x C R V -3 x C P ointer P ointer Justification Justification B lock B lock R S -0 x TM R S -0 x TM V -3 P H C O V -3 P H C O B lock B lock R S -0 x TM R S -0 x TM S H O S H O B lock B lock R S -4 S H x TM O R S -4 S H x TM O P rocessor P rocessor B lock B lock S -4 TM S -4 TM TelecomB us TelecomB us B lock B lock R A -3 x U R A -3 x U M apper/V -3 C M apper/V -3 C P H O P H O P rocessor P rocessor B lock B lock TxV -3 C TxV -3 C P ointer P ointer Justification Justification B lock B lock TxS -0 TM TxS -0 TM V -3 P H C O V -3 P H C O B lock B lock TxS -0 TM TxS -0 TM S H O S H O B lock B lock S R E E D S S R E E D S B lock B lock (P ary rim ) (P ary rim ) D 3/E S 3 D 3/E S 3 M apper M apper B lock B lock C hannel 1 To C hannels 2 –12 FromC hannels 2 –12 C lock S nthesizer B y lock C lock S nthesizer B y lock D 3/E S 3 D 3/E S 3 Jitter Jitter A ttenuator A ttenuator B lock B lock D 3/E S 3 D 3/E S 3 Fram er Fram er B lock B lock S R E E D S S R E E D S B lock B lock (A S P ) (A S P ) M icroprocessor Interface M icroprocessor Interface JTA Test P G ort JTA Test P G ort FIGURE 3. BLOCK DIAGRAM OF THE XRT94L43 WHEN CONFIGURED IN SDH/AU-3 MODE TxS -12 TS TxS -12 TS TO P H rocessor TO P H rocessor B lock B lock TxS N T O E TxS N T O E P H O P H O P rocessor P rocessor B lock B lock R S -1 x TS R S -1 x TS P ointer P ointer Justification Justification B lock B lock R S -1 x TS R S -1 x TS P H O P H O B lock B lock R S -1 x TS R S -1 x TS TO H TO H B lock B lock R S -12 TO x TS H R S -12 TO x TS H P rocessor P rocessor B lock B lock R S N T x O E R S N T x O E P H O P H O P rocessor P rocessor B lock B lock TxS -1 TS TxS -1 TS P ointer P ointer Justification Justification B lock B lock TxS -1 TS TxS -1 TS P H O P H O B lock B lock TxS -1 TS TxS -1 TS TO H TO H B lock B lock S -12 TS S -12 TS TelecomB us TelecomB us B lock B lock D 3/E S 3 D 3/E S 3 M apper M apper B lock B lock C hannel 1 To C hannels 2 –12 FromC hannels 2 –12 C lock S nthesizer B y lock C lock S nthesizer B y lock S R E E D S S R E E D S B lock B lock (P ary rim ) (P ary rim ) D 3/E S 3 D 3/E S 3 Jitter Jitter A ttenuator A ttenuator B lock B lock D 3/E S 3 D 3/E S 3 Fram er Fram er B lock B lock S R E E D S S R E E D S B lock B lock (A S P ) (A S P ) M icroprocessor Interface M icroprocessor Interface JTA Test P G ort JTA Test P G ort 3 XRT94L43 REV. 1.0.2 SONET/SDH OC-12 TO 12XDS3/E3 MAPPER PRODUCT FEATURES SONET TRANSMITTER • Generates and Transmits Standard STS-12/STM-4 data • Generates and Transmits either an STM-4/TUG-3 or STM-4/AU-3 signals for SDH applications • Conforms to ITU-T 1.432, ANSI T1.105 and Bellcore GR-253 Standards • Performs SONET frame insertion and accepts external frame synchronization • Performs Optional Transmit Data Scrambling • Permits the user to externally insert their own values for the POH and TOH into the outbound STS-12/STM-4 traffic • Generates transmit payload pointer (H1,H2) (fixed at 522) with NDF insertion • Inserts A1/A2 with optional error mask • Computes and inserts BIP-8 (B1,B2) with optional error mask • Generates and transmits REI-L and RDI-L either upon Software Command or automatically based upon errors and defects that are detected/declared by the SONET Receiver. • Permits the user to transmit the LOS pattern via Software Command. • Generates and transmits RDI-P and REI-P either upon Software Command or automatically based upon errors and defects that are detected/declared by the SONET Receiver. • Inserts the fixed-stuff columns, calculates and inserts the B3 byte value into each outbound STS-1 SPE/VC3 or STS-3c SPE/VC-4 SONET RECEIVER • Receives and processes standard STS-12/STM-4 signals • Receives and processes either an STM-4/TUG-3 or STM-4/AU-3 signal for SDH Applications • Permits the user to fully program the B2 Byte Error-rate thresholds for declaration and clearance of the SD and SF defect conditions • Provides section trace buffer with mismatch detection and invalid message detection • Performs SONET Frame Synchronization • Supports NDF, positive stuff and negative stuff for pointer processor • Performs receive data de-scrambling • Performs POH and TOH interpretation/extraction • Interprets payload pointer (H1,H2) • Extracts data communication channels from D1-D3 and D4-D12 • Declares and Clears the SEF (Severely Erred Frame), LOF (Loss of Frame) and LOS (Loss of Signal) defect conditions • Declares and clears the Line AIS (AIS-L) and the Line Remote Defect Indicator (RDI-L) defect conditions • Declares and Clears the Path - AIS (AIS-P), Loss of Pointer (LOP-P) and Path - Unequipped (UNEQ-P) defect conditions. • Supports either the Single-Bit or Extended form of RDI-P • Monitors the Path Signal Label and declares/clears the PLM-P defect condition 4 XRT94L43 SONET/SDH OC-12 TO 12XDS3/E3 MAPPER expected Path Trace Message REV. 1.0.2 • Contains 12 on-chip 64 byte Expected Receive Path Trace Message Buffer, in which the user will load in an • Contains 12 on-chip 64 byte Actual" Receive Path Trace Message Buffers, that will contain the actual Received Path Trace Message • The SONET Receiver will use the contents within both the Expected and Actual Receive Path Trace Message Buffers to either declare or clear the TIM-P defect condition • Computes and verifies the B3 bytes within each incoming STS-1 SPE/VC-3 or STS-3c SPE/VC-4 and increments on-chip Performance Monitoring registers each time it detects B3 byte errors. • Detects and Flags Line - Remote Error Indicator (REI-L) and Path - Remote Error Indicator (REI-P) events, and increments on-chip Performance Monitoring registers each time it detects REI-L or REI-P events • Computes and verifies both the B1 and B2 bytes within the incoming STS-12/STM-4 data-stream and increments on-chip Performance Monitoring registers each time it detects B1 or B2 byte errors MAPPER • Maps DS3 data into/De-maps DS3 data from an STS-1 SPE per the requirements in Telcordia GR-253CORE • Maps DS3/E3 data into/De-Maps DS3/E3 data from a VC-3 per ITU-T G.707 • Implements AU-3 to VC-3 multiplexing and de-multiplexing DS3 RECEIVE FRAMER • Offers off-line framing algorithm • Complies with the standards as: Bellcore TR-NWT-000499 and TR-NWT-000009 • Supports overhead extraction • Detects and flags LCV (Line Code Violations) and EXZ (Excessive Zero Events). • Reports and counts FEBE • HDLC controller complies with ITU-T Q.921 LAPD protocol • Provides Line and Local Loop-backs • Supports either the M13 or the C-bit Parity Framing formats • Supports B3ZS line decodi