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XRT94L33
Rev 2.0.0
3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER – ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER – ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER – ATM REG STERS
March 2007
GENERAL DESCRIPTION
The XRT94L33 is a highly integrated SONET/SDH terminator designed for E3/DS3/STS-1 mapping/de-mapping functions from either the STS-3 or STM-1 data stream. The XRT94L33 interfaces directly to the optical transceiver The XRT94L33 processes the section, line and path overhead in the SONET/SDH data stream and also performs ATM and PPP PHY-layer processing. The processing of path overhead bytes within the STS-1s or TUG-3s includes 64 bytes for storing the J1 bytes. Path overhead bytes can be accessed through the microprocessor interface or via serial interface. The XRT94L33 uses the internal E3/DS3 DeSynchronizer circuit with an internal pointer leak algorithm for clock smoothing as well as to remove the jitter due to mapping and pointer movements. These De-Synchronizer circuits do not need any external clock reference for its operation. The SONET/SDH transmit blocks allow flexible insertion of TOH and POH bytes through both Hardware and Software. Individual POH bytes for the transmitted SONET/SDH signal are mapped either from the XRT94L33 memory map or from external interface. A1, A2 framing pattern, C1 byte and H1, H2 pointer byte are generated. The SONET/SDH receive blocks receive SONET STS-3 signal or SDH STM-1 signal and perform the necessary transport and path overhead processing. The XRT94L33 provides a line side APS (Automatic Protection Switching) interface by offering redundant receive serial interface to be switched at the frame boundary. The XRT94L33 provides 3 Mappers for performing STS-1/VC-3 to STS-1/DS3/E3 mapping function, one for each STS-1/DS3/E3 framers. A PRBS test pattern generation and detection is implemented to measure the bit-error performance. A general-purpose microprocessor interface is included for control, configuration and monitoring. APPLICATIONS • • • Network switches Add/Drop Multiplexer W-DCS Digital Cross Connect Systems
FEATURES • Provides DS3/ E3 mapping/de-mapping for up to 3 tributaries through SONET STS-1 or SDH AU3 and/or TUG-3/AU-4 containers Generates and terminates SONET/SDH section, line and path layers Integrated SERDES with Clock Recovery Circuit Provides SONET descrambling frame scrambling and
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Integrated Clock Synthesizer that generates 155 MHz and 77.76 MHz clock from an external 12.96/19.44/77.76 MHz reference clock Integrated 3 E3/DS3/STS-1 De-Synchronizer circuit that de-jitter gapped clock to meet 0.05UIpp jitter requirements Access to Line or Section DCC Level 2 Performance Monitoring for E3 and DS3 Supports mixing of STS-1E and DS3 or E3 and DS3 tributaries UTOPIA Level 2 interface for ATM or level 2P for Packets E3 and DS3 framers for both Transmit and Receive directions Complete Transport/Section Overhead Processing and generation per Telcordia and ITU standards Single PHY and Multi-PHY operations supported Full line APS applications support for redundancy
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Loopback support for both SONET/SDH as well as E3/DS3/STS-1 Boundary scan capability with JTAG IEEE 1149 8-bit microprocessor interface 3.3 V ± 5% Power Supply; 5 V input signal tolerance -40°C to +85°C Operating Temperature Range
Available in a 504 Ball TBGA package
E Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * Fax (510) 668-7017 * www.exar.com
XRT94L33
3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER – ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER – ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER – ATM REG STERS Block Diagram of the XRT94L33
To OC3 Telecom Bus Interface SONET/SDH TOH SONET/SDH POH Boundry Scan
20 0 Rev2...0...0 200
To F.O.
OC3 TxRx
SDH MUX
Microprocessor Interface
SONET/SDH POH
DS3/E3 Mapper
Jitter Attenuator & Clock Sm oothing
DS3/E3 Fram er
ATM Processor PLCP PPP Processor
To DS3/E3 STS-1 Telecom Bus/ T3/E3/HDLC Intf
Telecom Bus Interface
Pointer Justify HDLC Controller STS-1 Tx/Rx TO H & POH
STS-1 Channel 0
SO NET/SDH PO H
DS3/E3 Mapper
Jitter Attenuator & Clock Sm oothing
DS3/E3 Fram er
ATM Processor PLCP PPP Processor UTOPIA II/IIp Interface
To DS3/E3 STS-1 Telecom Bus/ T3/E3/HDLC Intf
Telecom Bus Interface
Pointer Justify HDLC Controller STS-1 Tx/Rx TOH & POH
STS-1 Channel 1
SO NET/SDH PO H
DS3/E3 Mapper
Jitter Attenuator & Clock Sm oothing
DS3/E3 Fram er
ATM Processor PLCP PPP Processor
To DS3/E3 STS-1 Telecom Bus/ T3/E3/HDLC Intf
Telecom Bus Interface
Pointer Justify HDLC Controller STS-1 Tx/Rx TOH & POH STS-1 Channel 2
ORDERING INFORMATION
PART NUMBER XRT94L33IB PACKAGE TYPE 27 x 27 504 Lead TBGA OPERATING TEMPERATURE RANGE -40°C to +85°C
1.0 XRT94L33 REGISTERS FOR SONET ATM/PPP APPLICATIONS
1.1 THE OVERALL REGISTER MAP WITHIN THE XRT94L33 The XRT94L33 employs a direct Addressing Scheme. The Address Locations for each of the “Register Groups” (or Register pages) is presented in the Table below. Table 1: The Address Register Map for the XRT94L33
ADDRESS LOCATION 0x0000 – 0x00FF 0x0100 0x0101 Reserved Operation Control Register – Byte 3 Operation Control Register – Byte 2 0x00 0x00 REGISTER NAME OPERATION CONTROL BLOCK REGISTERS DEFAULT VALUE
2
XRT94L33
20 0 Rev2...0...0 200
3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER – ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER – ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER – ATM REG STERS
Reserved Operation Control Register – Byte 0 Operation Status Register – Byte 3 (Device ID) Operation Status Register – Byte 2 (Revision ID) Reserved Operation Interrupt Status Register – Byte 0 Reserved Operation Interrupt Enable Register – Byte 0 Reserved Operation Block Interrupt Status Register – Byte 1 Operation Block Interrupt Status Register – Byte 0 Reserved Operation Block Interrupt Enable Register – Byte 1 Operation Block Interrupt Enable Register – Byte 0 Reserved Reserved Mode Control Register – Byte 0 Reserved Loop-back Control Register – Byte 0 Channel Interrupt Indicator – Receive SONET POH Processor Block Reserved Channel Interrupt Indicator – DS3/E3 framer Block Channel Interrupt Indicator – Receive STS-1 POH Processor Block Channel Interrupt Indicator – Receive STS-1 TOH Processor Block Reserved Channel Interrupt Indicator – STS-1/DS3/E3 Mapper Block Reserved Reserved Reserved Reserved Reserved Reserved Interface Control Register – Byte 1 0x00 0x00 0xE3 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x11 0x00 0x00
0x0102 0x0103 0x0104 0x0105 0x0106 – 0x010A 0x010B 0x010C – 0x010E 0x010F 0x0110 – 0x0111 0x0112 0x0113 0x0114 – 0x0115 0x0116 0x0117 0x0118 – 0x0119 0x011A 0x011B 0x011C – 0x011E 0x011F 0x0120 0x0121 0x0122 0x0123 0x0124 0x0125 0x0126 0x0127 0x0128 0x0129 0x012A – 0x012F 0x0130 0x0131 0x0132
3
XRT94L33
3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER – ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER – ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER – ATM REG STERS
0x0133 0x0134 0x0135 0x0136 0x0137 0x0138 0x0139 0x013A 0x013B 0x013C 0x013D 0x013E 0x013F 0x0140 – 0x0146 0x0147 0x0148 – 0x0149 0x014A 0x014B 0x014C –0x014E 0x014F 0x0150 0x0151 –0x0152 0x0153 0x0154 0x0155 – 0x0156 0x0157 0x0158 0x0159 0x015A 0x015B 0x015C 0x015D Interface Control Register – Byte 0 STS-3/STM-1 Telecom Bus Control Register – Byte 3 STS-3/STM-1 Telecom Bus Control Register – Byte 2 Reserved STS-3/STM-1 Telecom Bus Control Register – Byte 0 Reserved Interface Control Register – Byte 2 – STS-3 Telecom Bus 2 Interface Control Register – Byte 1 – STS-3 Telecom Bus 1 Interface Control Register – Byte 0 – STS-3 Telecom Bus 0 Interface Control Register – STS-1 Telecom Bus Interrupt Register Interface Control Register – STS-1 Telecom Bus Interrupt Status Register Interface Control Register – STS-1 Telecom Bus Interrupt Register # 2 Interface Control Register – STS-1 Telecom Bus Interrupt Enable Register Reserved Operation General Purpose Input/Output Register Reserved Reserved Operation General Purpose Input/Output Direction Register – Byte 0 Reserved Reserved Operation Output Control Register – Byte 1 Reserved Operation Output Control Register – Byte 0 Operation Slow Speed Port Control Register – Byte 1 Reserved Operation Slow Speed Port Control Register –Byte 0 Operation – DS3/E3/STS-1 Clock Frequency Out of Range Detection – Direction Register Reserved Operation – DS3/E3/STS-1 Clock Frequency – DS3 Out of Range Detection Threshold Register Operation – DS3/E3/STS-1 Clock Frequency – STS-1/E3 Out of Range Detection Threshold Register Reserved Operation – DS3/E3/STS-1 Frequency Out of Range Interrupt Enable Register
20 0 Rev2...0...0 200
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
4
XRT94L33
20 0 Rev2...0...0 200
3--CHANNEL DS3///E3///STS--1 TO STS--3///STM--1 MAPPER – ATM REGIIISTERS 3-C HANNEL DS3 E 3 S TS-1 TO STS-3 S TM-1 MAPPER – ATM REG S TERS 3 CHANNEL DS3 E3 STS 1 TO STS 3 STM 1 MAPPER – ATM REG STERS
– Byte 0
0x015E 0x015F 0x0160 – 0x017F 0x0180 0x0181 0x0182 – 0x0193 0x0194 0x0195 0x0196 0x0197 0x0198 0x0199 0x019A 0x019B 0x019C 0x019D 0x019E 0x019F 0x01A0 – 0x01FF
Reserved Operation – DS3/E3/STS-1 Frequency Out of Range Interrupt Status Register – Byte 0 Reserved APS Mapping Register APS Control Register Reserved APS Status Register Reserved APS Status Register APS Status Register APS Interrupt Register Reserved APS Interrupt Register APS Interru
