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MARCH 2007
XRT94L31
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
REV. 1.0.1
GENERAL DESCRIPTION
The XRT94L31 is a highly integrated SONET/SDH terminator designed for E3/DS3/STS-1 mapping/demapping functions from either the STS-3 or STM-1 data stream. The XRT94L31 interfaces directly to the optical transceiver. The XRT94L31 processes the section, line and path overhead in the SONET/SDH data stream. The processing of path overhead bytes within the STS-1s or TUG-3s includes 64 bytes for storing the J1 bytes. Path overhead bytes can be accessed through the microprocessor interface or via serial interface. The XRT94L31 uses the internal E3/DS3 DeSynchronizer circuit with an internal pointer leak algorithm for clock smoothing as well as to remove the jitter due to mapping and pointer movements. These De-Synchronizer circuits do not need any external clock reference for its operation. The SONET/SDH transmit blocks allow flexible insertion of TOH and POH bytes through both Hardware and Software. Individual POH bytes for the transmitted SONET/SDH signal are mapped either from the XRT94L31 memory map or from external interface. A1, A2 framing pattern, C1 byte and H1, H2 pointer byte are generated. The SONET/SDH receive blocks receive SONET STS-3 signal or SDH STM-1 signal and perform the necessary transport and path overhead processing. The XRT94L31 provides a line side APS (Automatic Protection Switching) interface by offering redundant receive serial interface to be switched at the frame boundary. The XRT94L31 provides 3 mappers for performing STS-1/VC-3 to STS-1/DS3/E3 mapping function, one for each STS-1/DS3/E3 framers. A PRBS test pattern generation and detection is implemented to measure the bit-error performance. A general-purpose microprocessor interface is included for control, configuration and monitoring.
APPLICATIONS
• Network switches • Add/Drop Multiplexer • W-DCS Digital Cross Connect Systems
FEATURES
• Provides DS3/ E3 mapping/de-mapping for up to 3
tributaries through SONET STS-1 or SDH AU-3 and/or TUG-3/AU-4 containers
• Generates and terminates SONET/SDH section,
line and path layers
• Integrated SERDES with Clock Recovery Circuit • Provides SONET frame scrambling and
descrambling
• Integrated Clock Synthesizer that generates 155
MHz and 77.76 MHz clock from an external 12.96/ 19.44/77.76 MHz reference clock
• Integrated 3 E3/DS3/STS-1 De-Synchronizer circuit
that de-jitter gapped clock to meet 0.05UIpp jitter requirements
• Access to Line or Section DCC • Level 2 Performance Monitoring for E3 and DS3 • Supports mixing of STS-1E and DS3 or E3 and
DS3 tributaries
• E3 and DS3 framers for both Transmit and Receive
directions
• Complete Transport/Section Overhead Processing
and generation per Telcordia and ITU standards
• Single PHY and Multi-PHY operations supported • Full line APS support for redundancy applications • Loopback support for both SONET/SDH as well as
E3/DS3/STS-1
• Boundary scan capability with JTAG IEEE 1149·8bit microprocessor interface·
• 3.3 V ± 5% Power Supply; 5 V input signal
tolerance
• -40°C to +85°C Operating Temperature Range • Available in a 504 Ball TBGA package
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRT94L31
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC FIGURE 1. BLOCK DIAGRAM OF THE XRT94L31
REV. 1.0.1
Rx STS-1 Rx STS-1 TOH TOH Processor Processor Block Block
Tx Overhead Tx Overhead Data Input Data Input Interface Interface Block Block Tx HDLC Tx HDLC Controller Controller Block Block Rx HDLC Rx HDLC Controller Controller Block Block Rx Overhead Rx Overhead Data Output Data Output Interface Interface Block Block
Rx STS-1 Rx STS-1 POH POH Processor Processor Block Block
Tx SONET Tx SONET POH POH Processor Processor Block Block Tx DS3/E3 Tx DS3/E3 Mapper Mapper Block Block Rx DS3/E3 Rx DS3/E3 Mapper & Mapper & Jitter Attenuator Jitter Attenuator Block Block Rx SONET Rx SONET POH POH Processor Processor Block Block
Tx STS-3 Tx STS-3 TOH TOH Processor Processor Block Block Primary & Primary & Redundant Redundant Tx STS-3 Tx STS-3 PECL PECL Interface Interface Block Block
Tx STS-3 Tx STS-3 Telecom Telecom Bus Bus Block Block
Tx Payload Tx Payload Data Input Data Input Interface Interface Block Block Rx Payload Rx Payload Data Output Data Output Interface Interface Block Block
Tx DS3/E3 Tx DS3/E3 Framer Framer Block Block Rx DS3/E3 Rx DS3/E3 Framer Framer Block Block
Tx STS-1 Tx STS-1 TOH TOH Processor Processor Block Block
Tx STS-1 Tx STS-1 POH POH Processor Processor Block Block
Primary & Primary & Redundant Redundant Rx STS-3 Rx STS-3 TOH TOH Processor Processor Block Block Primary & Primary & Redundant Redundant CDR CDR Block Block
Rx STS-3 Rx STS-3 Telecom Telecom Bus Bus Block Block Primary & Primary & Redundant Redundant Rx STS-3 Rx STS-3 PECL PECL Interface Interface Block Block
Channel 0 Channel 1 Channel 2
ORDERING INFORMATION
PART NUMBER XRT94L31IB PACKAGE TYPE 27 x 27 504 Lead TBGA OPERATING TEMPERATURE RANGE -40°C to +85°C
2
XRT94L31
REV. 1.0.1
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN # SIGNAL NAME I/O TYPE DESCRIPTION
MICROPROCESSOR INTERFACE Y22 PCLK I TTL Microprocessor Interface Clock Input: This clock input signal is only used if the Microprocessor Interface has been configured to operate in one of the Synchronous Modes (e.g., Power PC 403 Mode). If the Microprocessor Interface is configured to operate in one of these modes, then it will use this clock signal to do the following.·
• To sample the CS*, WR*/R/W*, A[14:0], D[7:0], RD*/DS* and DBEN
input pins, and· To update the state of D[7:0] and the RDY/DTACK output signals. NOTES: 1. 2. The Microprocessor Interface can frequencies ranging up to 33MHz. work with mPCLK
This pin is inactive if the Microprocessor Interface has been configured to operate in either the Intel-Asynchronous or the Motorola-Asynchronousl Modes. In this case, tie this pin to GND.
AD25 AD23 AC21
PTYPE_0PTYPE_1P TYPE_2
I
TTL
Microprocessor Type Select input: These three input pins are used to configure the Microprocessor Interface block to readily support a wide variety of Microprocessor Interfaces. The relationship between the settings of these input pins and the corresponding Microprocessor Interface configuration is presented below. PTYPE[2:0] Microprocessor Interface Mode 000 Intel-Asynchronous Mode 001 Motorola - Asynchronous Mode 010 Intel X86 011 Intel I960 100 IDT3051/52 (MIPS) 101 Power PC 403 Mode 111 Motorola 860 Address Bus Input pins (Microprocessor Interface): These pins permit the Microprocessor to identify on-chip registers and Buffer/Memory locations (within the XRT94L31) whenever it performs READ and WRITE operations with the XRT94L31.
AD27 AB25 W23 Y24 AD26 AC25 AA24 Y23 AE24 AB20 AD22 AC20 AD21 AE23 AF24
PADDR_0 PADDR_1 PADDR_2 PADDR_3 PADDR_4 PADDR_5 PADDR_6 PADDR_7 PADDR_8 PADDR_9 PADDR_10 PADDR_11 PADDR_12 PADDR_13 PADDR_14
I
TTL
3
XRT94L31
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN # AD20 AC19 AE22 AG24 AE21 AD19 AF23 AE20 AF22 SIGNAL NAME PDATA_0 PDATA_1 PDATA_2 PDATA_3 PDATA_4 PDATA_5 PDATA_6 PDATA_7 PWR_L/R/W* I/O I/O TYPE TTL DESCRIPTION Bi-Directional Data Bus pins (Microprocessor Interface): These pins are used to drive and receive data over the bi-directional data bus, whenever the Microprocessor performs READ and WRITE operations with the Microprocessor Interface of the XRT94L31.
REV. 1.0.1
I
TTL
Write Strobe/Read-Write Operation Identifier: The function of this input pin depends upon which mode the Microprocessor Interface has been configured to operate in, as described below. Intel-Asynchronous Mode - WR* - Write Strobe Input: If the Microprocessor Interface is configured to operate in the Intel-Asynchronous Mode, then this input pin functions as the WR* (Active-Low WRITE Strobe) input signal from the Microprocessor. Once this activelow signal is asserted, then the input buffers (associated with the BiDirectional Data Bus pins, D[7:0]) will be enabled. The Microprocessor Interface will latch the contents on the Bi-Directional Data Bus (into the target register or address location, within the XRT94L31) upon the rising of this input. Motorola-Asynchronous Mode - R/W* - Read/Write Operation Identification Input Pin: If the Microprocessor Interface is operating in the Motorola-Asynchronous Mode, then this pin is functionally equivalent to the R/W* input pin. In the Motorola Mode, a READ operation occurs if this pin is held at a logic 1, coincident to a falling edge of the RD/DS* (Data Strobe) input pin. PowerPC 403 Mode - R/W* - Read/Write Operation Identification Input: If the Microprocessor Interface is configured to operate in the PowerPC 403 Mode, then this input pin will function as the Read/Write Operation Identification input pin. Anytime the Microprocessor Interface samples this input signal at a logic "Low" (while also sampling the CS* input pin "Low") upon the rising edge of PCLK, then the Microprocessor Interface will (upon the very same rising edge of PCLK) latch the contents of the Address Bus (A]14:0]) into the Microprocessor Interface circuitry, in preparation for this forthcoming READ operation. At some point (later in this READ operation) the Microprocessor will also assert the DBEN*/OE* input pin, and the Microprocessor Interface will then place the contents of the target register (or address location within the XRT94L31) upon the Bi-Directional Dat Bus pins (D[7:0]), where it can be read by the Microprocessor. Anytime the Microprocessor Interface samples this input signal at a logic "High" (while also sampling the CS* input pin at a logic "Low") upon the rising edge of PCLK, then the Microprocessor Interface will (upon the very same rising edge of PCLK) latch the contents of the Address Bus (A
