2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER

www.DataSheet4U.com xr PRELIMINARY XRT91L82 REV. P1.0.5 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER APRIL 2005 GENERAL DESCRIPTION The XRT91L82 is a fully integrated SONET/SDH transceiver for OC-48/STM16 applications supporting the use of Forward Error Correction (FEC) capability. The transceiver includes an on-chip Clock Multiplier Unit (CMU), which uses a high frequency PhaseLocked Loop (PLL) to generate the high-speed transmit serial clock from slower external clock references. It also provides Clock and Data Recovery (CDR) functions by synchronizing its on-chip Voltage Controlled Oscillator (VCO) to the incoming serial data stream. The chip provides serial-to-parallel and parallel-to-serial converters and 16-bit Differential LVDS/LVPECL, or Single-Ended LVPECL system interfaces in both receive and transmit directions. The transmit section includes a 16x9 Elastic Buffer (FIFO) to absorb any phase differences between the transmitter clock input and the internally generated transmitter reference clock. In the event of an overflow, an internal FIFO control circuit outputs an OVERFLOW indication. The FIFO under the control FIGURE 1. BLOCK DIAGRAM OF XRT91L82 of the FIFO_AUTORST register bit can automatically recover from an overflow condition. The operation of the device can be monitored by checking the status of the LOCKDET_CMU and LOCKDET_CDR output signals. An on-chip phase/frequency detector and charge-pump offers the ability to form a de-jittering PLL with an external VCXO that can be used in loop timing mode to clean up the recovered clock in the receive section. APPLICATIONS • SONET/SDH-based Transmission Systems • Add/Drop Multiplexers • Cross Connect Equipment • ATM and Multi-Service Switches, Routers and Switch/Routers • DSLAMS • SONET/SDH Test Equipment • DWDM Termination Equipment STS-48 TRANSCEIVER OVERFLOW FIFO_RST WP 16x9 FIFO TXOP/N PISO (Parallel Input Serial Output) Re-Timer TXSCLKOP/N TXDI[15:0]P/N 16 TXPCLKIP/N TXPCLKOP/N TXCLKO16P/N TXCLKO16SEL RLOOPP RP Div by 16 CMU DLOOP RLOOPS RXDO[15:0]P/N SIPO (Serial Input Parallel Output) CDR RXIP/N 16 RXPCLKOP/N DISRD DISRDCLK Div by 16 TDO TDI TCK TMS TRST JTAG Serial Microprocessor Hardware Control PFD & Charge Pump RLOOPS_PRBSCLR DLOOP LPTIME_NOJA Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com INTERM/VCXO_IN RXCAP1P RXCAP1N/CPOUT SE_REF SEREF_DIS PRBS_EN PRBS_ERR SDEXT POLARITY TXSWING TXSCLKOOFF LOCKDET_CMU PIO_CFG [1:0] LOCKDET_CDR REF1CLKP/N REF2CLKP/N REFREQSEL1 REFREQSEL0 CDRLCKREF CS SCLK SDI SDO HOST/HW XRES1P XRES1N INT RESET XRT91L82 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER xr REV. P1.0.5 FEATURES • 2.488 / 2.666 Gbps Transceiver • Targeted for SONET OC-48/SDH STM-16 Applications • Selectable full duplex operation between standard rate of 2.488 Gbps or Forward Error Correction rate of 2.666 Gbps • Single-chip fully integrated solution containing parallel-to-serial converter, clock multiplier unit (CMU), serialto-parallel converter, and clock data recovery (CDR) functions • 16-bit Differential LVDS/LVPECL, or Single-Ended LVPECL signaling data paths running at 155.52/166.63 Mbps using internal input termination for reduced passive components on board • Non-FEC and FEC rate REF1CLKP/N and REF2CLKP/N dual reference input ports • Supports 155.52/166.63MHz or 77.76/83.31MHz transmit and receive external reference input ports • Optional VCXO input port support multiple de-jittering modes in Host mode • On-chip phase detector and charge pump for external VCXO based de-jittering PLL • Internal FIFO decouples transmit parallel clock input and transmit parallel clock output • Provides Local, Remote Serial and Remote Parallel Loopback modes as well as Loop Timing mode • Diagnostics features include various lock detect functions and transmit CMU and receive CDR Lock Detect • Host mode serial microprocessor interface simplifies monitor and control • Meets Telcordia, ANSI and ITU-T jitter requirements including T1.105.03 - 2002 SONET Jitter Tolerance specification, GR-253 CORE, GR-253-ILR- SONET Jitter specifications. • Operates at 1.8V CMOS and CML Power with 3.3V I/O • 500mW Typical Power Dissipation using LVDS Interface • Package: 15 x 15 mm 196-pin STBGA • IEEE 1149.1 Compatable JTAG port PRODUCT ORDERING INFORMATION PRODUCT NUMBER XRT91L82IB PACKAGE TYPE 196 STBGA OPERATING TEMPERATURE RANGE -40° to +85° C C 2 REV. P1.0.5 xr xr xr xr FIGURE 2. 196 BGA PINOUT OF THE XRT91L82 (TOP VIEW) A GND RXIP RXIN VDD_CML TXON TXOP VDD_CML TXSCLKON TXSCLKOP VDD_CML REF2CLKP VDD_CML REF1CLKP GND B GND GND VDD_CML GND VDD_CML GND VDD_CML GND VDD_CML GND REF2CLKN GND REF1CLKN GND TXSCLKOOFF LOOPTM_NOJA C AVDD_RX SDEXT SEREFDIS TXCLKO16SEL LOCKDET_CDR LOCKDET_CMU DISRD D GND AVDD_RX PIO_CFG1 /PRBS_LOCK INTERM E RXCAP1P RXCAP1N F / CP_OUT G GND AVDD_RX VDD_IO RXDO0N RXDO0P GND TXDI15N TXDI15P VDD_IO TXDI13N GND VDD_CMOS GND VDD_CMOS GND VDD_CMOS GND VDD_CMOS GND GND PIO_CFG0 / VCXO_IN RESET VDD_CMOS GND VDD_CMOS / SDO PRBS_ERR POLARITY (I2C - SCL) TXDI14P GND XRES1N FIFO_RST OVERFLOW TDO TMS PRBS_EN / INT (I2C - SDA) DLOOP REFREQSEL0 GND XRES1P / SCLK TCK TDI / CS / SDI TXSWING DISRDCLK REFREQSEL1 AVDD_TX GND VDD_CML CDRLCKREF VDD_CML AVDD_TX RLOOPS_PRBSCLR PRELIMINARY XRT91L82 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER TXDI13P TXDI14N AVDD_TX GND H AVDD_RX GND RXDO1N RXDO1P GND RXDO2N RXDO2P RXDO3P TXDI11P GND TXDI12N TXDI12P GND AVDD_TX 3 J VDD_IO RXDO4N RXDO4P VDD_CMOS RXDO5N RXDO5P VDD_CMOS RXDO3N TXDI11N TXDI9P VDD_IO TXDI10N TXDI10P TXDI8P K RXDO6N RXDO6P VDD_IO RXDO7N RXDO7P VDD_IO RXDO8N RXDO8P VDD_IO TXDI9N TXDI7N TXDI7P VDD_IO TXDI8N L GND RXDO9N RXDO9P GND RXDO10N RXDO10P SE_REF RXDO11P TXDI5N TXDI5P GND TXDI6N TXDI6P GND M RXDO12N RXDO12P VDD_IO RXDO13N RXDO13P VDD_CMOS RXDO14P RXDO11N VDD_CMOS TXDI3N TXDI3P VDD_CMOS TXDI4N TXDI4P N VDD_IO HOST/HW TRST VDD_IO RXDO15N RXDO15P RXDO14N GND TXDI1N TXDI1P VDD_IO TXDI2N TXDI2P VDD_IO P TXCLKO16NTXCLKO16P GND RXPCLKON RXPCLKOP GND TXPCLKON TXPCLKOP GND TXPCLKIN TXPCLKIP GND TXDI0N TXDI0P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 XRT91L82 REV. P1.0.5 PRELIMINARY TABLE OF CONTENTS xr 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER GENERAL DESCRIPTION .................................................................................................1 APPLICATIONS ...........................................................................................................................................1 FIGURE 1. BLOCK DIAGRAM OF XRT91L82 ...................................................................................................................................... 1 FEATURES ......................................................................................................................................................2 PRODUCT ORDERING INFORMATION ..................................................................................................2 FIGURE 2. 196 BGA PINOUT OF THE XRT91L82 (TOP VIEW).......................................................................................................... 3 TABLE OF CONTENTS ............................................................................................................ I PIN DESCRIPTIONS ..........................................................................................................4 COMMON CONTROL .....................................................................................................................................4 TRANSMITTER SECTION ..................................................................................................................................8 RECEIVER SECTION .......................................................................................................................................11 SERIAL MICROPROCESSOR INTERFACE .............................................................................................14 ...................................................................................................................................................................14 JTAG ..........................................................................................................................................................15 1.0 FUNCTIONAL DESCRIPTION .............................................................................................................16 1.1 HARDWARE MODE VS. HOST MODE .......................................................................................................... 16 1.2 CLOCK INPUT REFERENCE ......................................................................................................................... 16 TABLE 1: REFERENCE FREQUENCY OPTIONS (NORMAL MODE/ FEC RATE)...................................................................................... 16 1.3 ALTERNATE CLOCK INPUT REFERENCE (HOST MODE ONLY) .............................................................. 16 TABLE 2: ALTERNATE REFERENCE FREQUENCY OPTIONS (NORMAL MODE/ FEC RATE) ................................................................... 17 1.4 DATA LATENCY ............................................................................................................................................. 17 TABLE 3: DATA INGRESS TO DATA EGRESS LATENCY ....................................................................................................................... 17 1.5 FORWARD ERROR CORRECTION (FEC) .................................................................................................... 17 FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF FORWARD ERROR CORRECTION ...................................................