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PRELIMINARY
XRT91L81
REV. P1.0.3
2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
JANUARY 2004
GENERAL DESCRIPTION
The XRT91L81 is a fully integrated SONET/SDH transceiver block for applications in SONET OC-48 allowing the use of Forward Error Correction (FEC) capability. The transceiver includes an on-chip Clock Multiplier Unit (CMU), which uses a high frequency Phase-Locked Loop (PLL) to generate the highspeed transmit serial clock from slower external clock references. It also provides Clock and Data Recovery (CDR) functions by synchronizing its on-chip Voltage Controlled Oscillator (VCO) to the incoming serial data stream. The chip provides serial-to-parallel and parallel-to-serial converters and 4-bit LVDS system interfaces in both receive and transmit directions. The transmit section includes a 4x9 Elastic Buffer (FIFO) to absorb any phase differences between the transmitter input clock and the internally generated transmitter reference clock. In the event of an overflow, an internal FIFO control circuit outputs an OVERFLOW indication. The FIFO under the control of the AUTORST pin can automatically recover from FIGURE 1. BLOCK DIAGRAM OF THE XRT91L81
an overflow condition. The operation of the device can be monitored by checking the status of the LOCKDET and LOSDET output signals. An on-chip phase/frequency detector and charge-pump offers the ability to form a de-jittering PLL with an external VCXO that can be used in loop timing mode to clean up the recovered clock in the receive section. APPLICATIONS
• SONET/SDH-based Transmission Systems • Add/Drop Multiplexers • Cross Connect Equipment • ATM and Multi-Service Switches, Routers and
Switch/Routers
• DSLAMS • SONET/SDH Test Equipment • DWDM Termination Equipment • Optical Modules and Sub-Systems
OC-48 TRANSCEIVER
FIFO_RST FIFO_AUTORST TxDI0P/N TxDI1P/N TxDI2P/N TxDI3P/N TxCLKIP/N
TXPCLKOP/N TXCLKO16P/N TRITXCLKO16
WP 4x9 FIFO PISO (Parallel Input Serial Output) TXOP/N
Re-Timer
RP
0 1
TXO2P/N
CMU RLOOPP DLOOP RLOOPS TXO2DIS TXO2SEL
RxDO0P/N RxDO1P/N RxDO2P/N RxDO3P/N RxCLKP/N RXCLK16P/N DISRD
SIPO (Serial Input Parallel Output)
0 CDR 1
RXI0P/N
RXI1P/N RXSEL TRIRXD REXT
Serial Microprocessor
Hardware Control
PFD & Charge Pump
RLOOPS RLOOPP DLOOP LPTIME_JA LPTM_NO_JA LOOPBW
LOCKDET_CMU
LOCKDET_CDR
LOSDET LOSEXT POLARITY
TEST
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
REFCLKP/N VCXO_INP/N REFFREQSEL VCXO_SEL VCXO_LOCKEN VCXO_LOCK CPOUT
OVERFLOW
CS SCLK SDI SDO Host/Hw
INT Reset
XRT91L81 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
REV. P1.0.3
PRELIMINARY
• Selectable full duplex operation between standard
rate of 2.488 Gbps or Forward Error Correction rate of 2.666 Gbps
FEATURES
• 2.488 / 2.666 Gbps Transceiver • Single-chip fully integrated solution containing
parallel-to-serial converter, clock multiplier unit (CMU), serial-to-parallel converter, limiting amplifier and clock data recovery (CDR) functions
• 4-bit LVDS data paths at 622/666 MHz complies
with OIF SFI-4 Implimentation Agreement
• Internal FIFO decouples transmit input and output
clocks
• Host
mode serial microprocessor simplifies monitor and control
interface
• Provides support for dual fiber rings • Integrated limiting amplifier accepts differential
inputs down to 10mVp-p
• Tx CMU and Rx CDR lock detect • Provides Local, Remote and Split Loop-Back
modes as well as Loop Timing mode
• Diagnostics features include various lock detect
functions
• Separate reference and VCXO input ports support
multiple de-jittering modes
• Meets
• On-chip phase detector and charge pump for
external VCXO based de-jittering PLL
Telcordia, requirements
ANSI
and
ITU-T
jitter
• Targeted
for Applications
SONET
OC-48/SDH
STM-16
• Operates at 1.8V with 3.3V I/O • 600mW Typical Power Dissipation • Package: 12 x 12 mm 196-pin STBGA
PRODUCT ORDERING INFORMATION
PRODUCT NUMBER XRT91L81IB PACKAGE TYPE 196 STBGA OPERATING TEMPERATURE RANGE -40°C to +85°C
2
A
RXSEL CSB RLOOPP DGND VDD3.3 DISRD DGND DGND RXCLK16P RXCLK16N VDD3.3 SDI AGND_RX Reset DGND DGND DGND DGND LOSEXT DLOOP VDD1.8 DGND SCLK VDD3.3
REXT
RXD3P
PRELIMINARY
B
AGND_RX RLOOPS INTB TRIRXD AGND_RX POLARITY LOSDET LPTIME_JA LOCKDET-CDR SDO HOST/HWB
AGND_RX
RXD3N
C
AGND_RX VDD3.3 VDD3.3 AVDD3.3_RX AVDD1.8_RX AVDD1.8_RX AVDD1.8_RX AGND_RX AVDD1.8_RX VDD3.3 VDD1.8
RXI0P
RXD2P
RXD1P
D
AGND_RX TGND AVDD3.3_RX AGND_RX TGND TGND TGND TGND TGND VDD3.3
RXI0N
RXD2N
RXD1N
E
AGND_RX AVDD1.8_RX AGND_RX TGND TGND TGND TGND TGND TGND
AGND_RX
VDD1.8
RXD0P
RXCLKP
F
AGND_RX AVDD1.8_RX AGND_RX TGND TGND TGND TGND TGND TGND
RXI1N
DGND
DGND
RXD0N
RXCLKN
G
AGND_RX AGND_RX AGND_RX TGND TGND TGND TGND TGND
RXI1P
DGND
DGND
DGND
DGND
H
AGND_TX AGND_TX AVDD1.8_TX TGND TGND TGND TGND
AGND_RX
TGND
DGND
DGND
TXDI0P
TXCLKIP
TABLE 1: 196 BGA PINOUT OF THE XRT91L81 (TOP VIEW)
XRT91L81 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
3
TXON AGND_TX AGND_TX TGND TGND TGND TGND TXOP DGND AGND_TX AGND_TX AVDD1.8_TX AVDD1.8_TX AVDD1.8_TX AVDD3.3_TX AVDD1.8_TX AGND_TX AGND_TX VCXO_SEL LOOPBW NC LOCKDET-CMU TXO2_SEL VCXO_INN AGND_TX REFCLKN AGND_TX AGND_TX CPOUT 2 3 4 5 6 7 8
J
AVDD3.3_TX
TGND
TGND
DGND
DGND
TXDI0N
TXCLKIN
K
TXO2P
TGND
TGND
VDD1.8
DGND
TXDI2P
TXDI1P
L
TXO2N
VDD1.8
VDD1.8
DGND
DGND
TXDI2N
TXDI1N
M
AGND_TX
VDD1.8
VDD1.8
VDD1.8
TRITXCLKO16 OVERFLOW TXDI3P
N
TXO2DIS
VCXO_LOCK AVDD1.8_TX TXCLKO16P TXCLKO16N FIFO_AUTORST FIFO_RESET TXDI3N
P
REFFREQSEL LPTIME_NO_JA VCXO_LOCKEN VCXO_INP AVDD3.3_TX REFCLKP
AVDD3.3_TX TXPCLKOP TXPCLKON
DGND
VDD3.3
VDD3.3
1
9
10
11
12
13
14
REV. P1.0.3
XRT91L81 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
REV. P1.0.3
PRELIMINARY
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................1
APPLICATIONS ...........................................................................................................................................1
FIGURE 1. BLOCK DIAGRAM OF THE XRT91L81 ............................................................................................................................... 1 FEATURES ......................................................................................................................................................2
PRODUCT ORDERING INFORMATION ..................................................................................................2
TABLE 1: 196 BGA PINOUT OF THE XRT91L81 (TOP VIEW) ........................................................................................................... 3
TABLE OF CONTENTS ............................................................................................................I PIN DESCRIPTIONS ..........................................................................................................4
SERIAL MICROPROCESSOR INTERFACE............................................................................................................4 HARDWARE CONTROL .....................................................................................................................................5 TRANSMITTER SECTION ..................................................................................................................................6 RECEIVER SECTION .........................................................................................................................................8 POWER AND GROUND ..................................................................................................................................10 NO CONNECTS .............................................................................................................................................11 1.0 FUNCTIONAL DESCRIPTION .............................................................................................................12
1.1 HARDWARE MODE VS. HOST MODE .......................................................................................................... 12 1.2 INPUT CLOCK REFERENCE ......................................................................................................................... 12 1.3 FORWARD ERROR CORRECTION (FEC) .................................................................................................... 12
TABLE 2: REFERENCE FREQUENCY OPTIONS (NORMALMODE/FEC) ................................................................................................ 12 FIGURE 2. SIMPLIFIED BLOCK DIAGRAM OF FORWARD ERROR CORRECTION .................................................................................... 12
2.0 RECEIVE SECTION .............................................................................................................................13
2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 13
FIGURE 3. RECEIVE SERIAL INPUT INTERFACE BLOCK ..................................................................................................................... 13
2.2 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 14 2.3 LOSS OF SIGNAL .......................................................................................................................................... 14 2.4 RECEIVE SERIAL INPUT TO PARALLEL OUTPUT (SIPO) ......................................................................... 14
FIGURE 4. SIMPLIFIED BLOCK DIAGRAM OF SIPO ........................................................................................................................... 14
2.5 RECEIVE PARALLEL OUTPUT INTERFACE ..................................................
