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PRELIMINARY
XRT91L80
REV. P1.0.4
2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
MARCH 2005
GENERAL DESCRIPTION
The XRT91L80 is a fully integrated SONET/SDH transceiver for SONET OC-48 allowing the use of Forward Error Correction (FEC) capability. The transceiver includes an on-chip Clock Multiplier Unit (CMU), which uses a high frequency Phase-Locked Loop (PLL) to generate the high-speed transmit serial clock from slower external clock references. It also provides Clock and Data Recovery (CDR) functions by synchronizing its on-chip Voltage Controlled Oscillator (VCO) to the incoming serial data stream. The chip provides serial-to-parallel and parallel-toserial converters and 4-bit LVDS system interfaces in both receive and transmit directions. The transmit section includes a 4x9 Elastic Buffer (FIFO) to absorb any phase differences between the transmitter input clock and the internally generated transmitter reference clock. In the event of an overflow, an internal FIFO control circuit outputs an OVERFLOW indication. The FIFO under the control of the FIGURE 1. BLOCK DIAGRAM OF XRT91L80
AUTORST pin can automatically recover from an overflow condition. The operation of the device can be monitored by checking the status of the LOCKDET and LOSDET output signals. An on-chip phase/ frequency detector and charge-pump offers the ability to form a de-jittering PLL with an external VCXO that can be used in loop timing mode to clean up the recovered clock in the receive section. APPLICATIONS
• SONET/SDH-based Transmission Systems • Add/Drop Multiplexers • Cross Connect Equipment • ATM and Multi-Service Switches, Routers and
Switch/Routers
• DSLAMS • SONET/SDH Test Equipment • DWDM Termination Equipment
OC-48 TRANSCEIVER
FIFO_RST FIFO_AUTORST TxDI0P/N TxDI1P/N TxDI2P/N TxDI3P/N TxCLKIP/N
TXPCLKOP/N TXCLKO16P/N TRITXCLKO16
WP 4x9 FIFO PISO (Parallel Input Serial Output) TXOP/N
Re-Timer
RP
CMU RLOOPP DLOOP RLOOPS
RxDO0P/N RxDO1P/N RxDO2P/N RxDO3P/N RxCLKP/N RXCLK16P/N DISRD
SIPO (Serial Input Parallel Output)
CDR
RXIP/N
TRIRXD
TDO TDI TCK TMS TRST
JTAG
Serial Microprocessor
Hardware Control
PFD & Charge Pump
RLOOPS RLOOPP DLOOP LPTIME_JA LPTM_NO_JA LOOPBW
LOCKDET_CMU
LOCKDET_CDR
LOSDET LOSEXT POLARITY
TEST
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
REFCLKP/N VCXO_INP/N REFFREQSEL VCXO_SEL VCXO_LOCKEN VCXO_LOCK CPOUT
OVERFLOW
CS SCLK SDI SDO Host/Hw
INT Reset
XRT91L80 PRELIMINARY 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER FEATURES
xr
REV. P1.0.4
• 2.488 / 2.666 Gbps Transceiver • Single-chip fully integrated solution containing parallel-to-serial converter, clock multiplier unit (CMU), serialto-parallel converter, limiting amplifier and clock data recovery (CDR) functions
• Host mode serial microprocessor interface simplifies monitor and control • Separate reference and VCXO input ports support multiple de-jittering modes • On-chip phase detector and charge pump for external VCXO based de-jittering PLL • Targeted for SONET OC-48/SDH STM-16 Applications • Selectable full duplex operation between standard rate of 2.488 Gbps or Forward Error Correction rate of
2.666 Gbps
• 4-bit LVDS data paths at 622/666 MHz compliant with OIF SFI-4 Implimentation Agreement • Internal FIFO decouples transmit input and output clocks • Tx CMU and Rx CDR lock detect • Provides Local, Remote and Split Loop-Back modes as well as Loop Timing mode • Diagnostics features include various lock detect functions • Meets Telcordia, ANSI and ITU-T jitter requirements • Operates at 1.8V with 3.3V I/O • 420mW Typical Power Dissipation • Package: 12 x 12 mm 196-pin STBGA • IEEE 1149.1 Compatable JTAG port PRODUCT ORDERING INFORMATION
PRODUCT NUMBER XRT91L80IB PACKAGE TYPE 196 STBGA OPERATING TEMPERATURE RANGE -40° to +85° C C
2
REV. P1.0.4
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FIGURE 2. 196 BGA PINOUT OF THE XRT91L80 (TOP VIEW)
A
AGND_RX
TRST
DISRD
NC
DGND
RXCLK16P
RXCLK16N
VDD3.3
SDI
CS
RLOOPP
DGND
VDD1.8
RXD3P
B
AGND_RX
AGND_RX
DGND
NC
LOSEXT
DLOOP
VDD1.8
DGND
SCLK
RESET
TDO
DGND
VDD1.8
RXD3N
C
RXI0P
AGND_RX
AGND_RX
POLARITY
LOSDET
LPTIME_JA LOCKDET-CDR
SDO
HOST/HW
RLOOPS
INT
TRIRXD
RXD2P
RXD1P
D
RXI0N
AGND_RX
AVDD3.3_RX AVDD1.8_RX AVDD1.8_RX AVDD1.8_RX
AGND_RX
AVDD1.8_RX
VDD3.3
VDD3.3
VDD3.3
VDD1.8
RXD2N
RXD1N
E
AGND_RX
AGND_RX
AVDD3.3_RX
AGND_RX
TGND
TGND
TGND
TGND
TGND
TGND
VDD3.3
VDD1.8
RXD0P
RXCLKP
F
RXN
AGND_RX
AVDD1.8_RX
AGND_RX
TGND
TGND
TGND
TGND
TGND
TGND
DGND
DGND
RXD0N
RXCLKN
PRELIMINARY
XRT91L80 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
G
RXP
AGND_RX
AVDD1.8_RX
AGND_RX
TGND
TGND
TGND
TGND
TGND
TGND
DGND
DGND
DGND
DGND
H AGND_RX
AGND_RX
AGND_RX
AGND_RX
TGND
TGND
TGND
TGND
TGND
TGND
DGND
DGND
TXDI0P
TXCLKIP
3
J AVDD1.8_TX
AGND_TX
AGND_TX
AVDD1.8_TX
TGND
TGND
TGND
TGND
TGND
TGND
DGND
DGND
TXDI0N
TXCLKIN
K
TXOP
AGND_TX
AGND_TX
AGND_TX
TGND
TGND
TGND
TGND
TGND
TGND
VDD1.8
DGND
TXDI2P
TXDI1P
L
TXON
AGND_TX
DGND
AGND_TX
AGND_TX AVDD1.8_TX AVDD1.8_TX AVDD1.8_TX
VDD1.8
VDD1.8
DGND
DGND
TXDI2N
TXDI1N
M AGND_TX
AVDD1.8_TX
AVDD1.8_TX
AGND_TX
AGND_TX
VCXO_SEL
LOOPBW
TDI
VDD1.8
VDD1.8
VDD1.8
TRITXCLKO16 OVERFLOW TXDI3P
N
TMS
LOCKDET-CMU
TCK
VCXO_INN
AGND_TX
REFCLKN
AGND_TX
VCXO_LOCK AVDD1.8_TX TXCLKO16P TXCLKO16N FIFO_AUTORST FIFO_RESET TXDI3N
P REFFREQSEL LPTIME_NO_JA VCXO_LOCKEN VCXO_INP AVDD3.3_TX REFCLKP
AGND_TX
CPOUT
AVDD3.3_TX TXPCLKOP TXPCLKON
DGND
VDD1.8
VDD1.8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
XRT91L80 PRELIMINARY 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
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REV. P1.0.4
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................1
APPLICATIONS ...........................................................................................................................................1
FIGURE 1. BLOCK DIAGRAM OF XRT91L80 ...................................................................................................................................... 1 FEATURES ......................................................................................................................................................2
PRODUCT ORDERING INFORMATION ..................................................................................................2
FIGURE 2. 196 BGA PINOUT OF THE XRT91L80 (TOP VIEW).......................................................................................................... 3
TABLE OF CONTENTS ............................................................................................................ I PIN DESCRIPTIONS ..........................................................................................................4
SERIAL MICROPROCESSOR INTERFACE............................................................................................................4 HARDWARE CONTROL .....................................................................................................................................5 TRANSMITTER SECTION ..................................................................................................................................6 RECEIVER SECTION .........................................................................................................................................8 POWER AND GROUND ....................................................................................................................................9 NO CONNECTS .............................................................................................................................................10 JTAG ..........................................................................................................................................................11 1.0 FUNCTIONAL DESCRIPTION .............................................................................................................12
1.1 HARDWARE MODE VS. HOST MODE .......................................................................................................... 12 1.2 INPUT CLOCK REFERENCE ......................................................................................................................... 12
TABLE 1: REFERENCE FREQUENCY OPTIONS (NORMALMODE/FEC) ................................................................................................ 12
1.3 FORWARD ERROR CORRECTION (FEC) .................................................................................................... 12
FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF FORWARD ERROR CORRECTION .................................................................................... 12
2.0 RECEIVE SECTION .............................................................................................................................13
2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 13
FIGURE 4. RECEIVE SERIAL INPUT INTERFACE BLOCK ..................................................................................................................... 13
2.2 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 14 2.3 LOSS OF SIGNAL .......................................................................................................................................... 14 2.4 RECEIVE SERIAL INPUT TO PARALLEL OUTPUT (SIPO) ......................................................................... 14
FIGURE 5. SIMPLIFIED BLOCK DIAGRAM OF SIPO .....................................................................................................................
