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NOVEMBER 2006
PRELIMINARY
XRT91L32
REV. 1.0.2
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
GENERAL DESCRIPTION
The XRT91L32 is a fully integrated SONET/SDH transceiver for SONET/SDH 622.08 Mbps STS-12/ STM-4 or 155.52 Mbps STS-3/STM-1 applications. The transceiver includes an on-chip Clock Multiplier Unit (CMU), which uses a high frequency PhaseLocked Loop (PLL) to generate the high-speed transmit serial clock from a slower external clock reference. It also provides Clock and Data Recovery (CDR) function by synchronizing its on-chip Voltage Controlled Oscillator (VCO) to the incoming serial data stream. The internal CDR unit can be disabled and bypassed in lieu of an externally recovered received clock from the optical module. Either the internally recovered clock or the externally recovered clock can be used for loop timing applications. The chip provides serial-to-parallel and parallel-to-serial converters using an 8-bit wide LVTTL system interface in both receive and transmit directions. The transmit section includes an option to accept a FIGURE 1. BLOCK DIAGRAM OF XRT91L32
parallel clock signal from the framer/mapper to synchronize the transmit section timing. The device can internally monitor Loss of Signal (LOS) condition and automatically mute received data upon LOS. An on-chip SONET/SDH frame byte and boundary detector and frame pulse generator offers the ability recover SONET/SDH framing and to byte align the receive serial data stream into the 8-bit parallel bus. APPLICATIONS
• SONET/SDH-based Transmission Systems • Add/Drop Multiplexers • Cross Connect Equipment • ATM and Multi-Service Switches, Routers and
Switch/Routers
• DSLAMS • SONET/SDH Test Equipment • DWDM Termination Equipment
XRT91L32
STS-12/STM-4 or STS-3/STM-1 TRANSCEIVER
TXDI[7:0]
8
TXPCLK_IO REFCLKP/N TTLREFCLK
PISO (Parallel Input Serial Output)
ENB
Re-Timer
TXOP/N
MUX Div by 8
ENB
XOR
CMU DLOOP
RLOOPS
ALOOP
MUX
CDRAUXREFCLK
MUX
RXDO[7:0]
SIPO (Serial Input Parallel Output)
CDR MUX
RXIP/N
8
XRXCLKIP/N RXPCLKO Div by 8
Control Block Loop Filters
Clock Control
CAP1N
CAP2N
CAP1P
CAP2P
DLOSDIS
LOSEXT
OOF FRAMEPULSE
CDRDIS
CMUFREQSEL
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
STS-12/STS-3
CDRREFSEL
LOOPTIME
PIO_CTRL
RLOOPS
DLOOP
ALOOP
Reset
XRT91L32 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER FEATURES
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REV. 1.0.2
• Targeted for SONET STS-12/STS-3 and SDH STM-4/STM-1 Applications • Selectable full duplex operation between STS-12/STM-4 standard rate of 622.08 Mbps or STS-3/STM-1
155.52 Mbps
• Single-chip fully integrated solution containing parallel-to-serial converter, clock multiplier unit (CMU), serialto-parallel converter, clock data recovery (CDR) functions, and a SONET/SDH frame and byte boundary detection circuit
• Ability to disable and bypass onchip CDR for external based received reference clock recovery thru
Differential LVPECL input pins XRXCLKIP/N
• 8-bit LVTTL parallel data bus paths running at 77.76 Mbps in STS-12/STM-4 or 19.44 Mbps in STS-3/STM-1
mode of operation
• Uses Differential LVPECL or Single-Ended LVTTL CMU reference clock frequencies of either 19.44 MHz or
77.76 MHz for both STS-12/STM-1 or STS-3/STM-1 operations
• Optional use of 77.76 MHz Single-Ended LVTTL input for independent CDR reference clock operation • Able to Detect and Recover SONET/SDH frame boundary and byte align received data on the parallel bus • Diagnostics features include LOS monitoring and automatic received data mute upon LOS • Provides Local, Remote and Split Loop-Back modes as well as Loop Timing mode • Optional flexibility to re-configure the transmit parallel bus clock output to a clock input and accept timing
signal from the framer/mapper device to permit the framer/mapper device time domain to be synchronized with the transceiver transmit timing.
• Meets Telcordia, ANSI, Bellcore TR-NWT-000253 and GR-253-CORE, and G.783 ITU-T jitter requirements • Operates at 3.3V with 3.3V I/O • Less than 660mW in STS-3/STM-1 mode or 800mW in STS-12/STM-4 mode Typical Power Dissipation • Package: 10 x 10 x 2.0 mm 100-pin QFP
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REV. 1.0.2
XRT91L32 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
FIGURE 2. 100 QFP PIN OUT OF THE XRT91L32 (TOP VIEW)
DLOOP VDD3.3 CDRREFSEL STS12/STS3 NC TXDI0 TXDI1 GND TXDI2 TXDI3 NC TXIN4 TXDI5 GND TXDI6 TXDI7 GND NC TXPCLK_IO PIO_CTRL/VDD
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
RLOO PS VDD3.3 ALO OP R ESET LO OPTIME NC NC CMUFREQ SEL VD D_PEC L TXO P TXO N GND NC NC VD D_PEC L NC DLOSDIS GND XRXCLKIP XRXCLKIN VDD_PECL OOF CDRDIS RXIP RXIN NC NC VDD3.3 REFCLKP REFCLKN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
XRT91L32
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NC NC NC NC VDD3.3 GND NC NC GND AGND_RX AGND_RX AVDD3.3_RX AVDD3.3_RX AVDD3.3_RX CAP2P CAP2N CAP1N CAP1P AVDD3.3_TX NC AGND_TX AGND_TX VDD3.3 NC TTLREFCLK GND VDD3.3 LOSEXT NC CDRAUXREFCLK
ORDERING INFORMATION
PART NUMBER XRT91L32IQ-F PACKAGE 100 Pin QFP OPERATING TEMPERATURE RANGE -40°C to +85°C
VDD3.3 NC NC GND RXDO0 RXD01 GND RXDO2 RXDO3 GND RXDO4 RXDO5 GND RXDO6 RXDO7 GND RXPCLKO FRAMEPULSE VDD3.3 NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
3
XRT91L32
REV. 1.0.2
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STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................1
APPLICATIONS ...........................................................................................................................................1
FIGURE 1. BLOCK DIAGRAM OF XRT91L32 ...................................................................................................................................... 1 FEATURES ......................................................................................................................................................2 FIGURE 2. 100 QFP PIN OUT OF THE XRT91L32 (TOP VIEW).......................................................................................................... 3
ORDERING INFORMATION.....................................................................................................................3 TABLE OF CONTENTS ............................................................................................................ I
PIN DESCRIPTIONS ..........................................................................................................4
.....................................................................................................................................................................4 HARDWARE CONTROL ....................................................................................................................................4 TRANSMITTER SECTION ..................................................................................................................................6 RECEIVER SECTION ........................................................................................................................................8 POWER AND GROUND ....................................................................................................................................9 1.0 FUNCTIONAL DESCRIPTION .............................................................................................................11
1.1 STS-12/STM-4 AND STS-3/STM-1 MODE OF OPERATION ......................................................................... 11 1.2 CLOCK INPUT REFERENCE FOR CLOCK MULTIPLIER (SYNTHESIZER) UNIT ...................................... 11
TABLE 1: CMU REFERENCE FREQUENCY OPTIONS (DIFFERENTIAL OR SINGLE-ENDED) ................................................................... 11
1.3 DATA LATENCY ............................................................................................................................................. 11
TABLE 2: DATA INGRESS TO DATA EGRESS LATENCY ....................................................................................................................... 11
2.0 RECEIVE SECTION .............................................................................................................................12
2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 12
FIGURE 3. RECEIVE SERIAL INPUT INTERFACE BLOCK ..................................................................................................................... 12
2.2 RECIEVE SERIAL DATA INPUT TIMING ...................................................................................................... 13
FIGURE 4. RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING DIAGRAM .......................................................................................... 13 TABLE 3: RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING (STS-12/STM-4 OPERATION) ............................................................. 13 TABLE 4: RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING (STS-3/STM-1 OPERATION) ............................................................... 13
2.3 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 14
TABLE 5: CLOCK DATA RECOVERY UNIT REFERENCE CLOCK SETTINGS ............................................................................................ 14 TABLE 6: CLOCK AND DATA RECOVERY UNIT PERFORMANCE .......................................................................................................... 15 2.3.1 INTERNAL CLOCK AND DATA RECOVERY BYPASS ............................................................................................ 15 FIGURE 5. INTERNAL CLOC
