www.DataSheet4U.com
xr
DEC 2006
Preliminary
XRT91L31
REV. 1.0.2
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
GENERAL DESCRIPTION
The XRT91L31 is a fully integrated SONET/SDH transceiver for SONET/SDH 622.08 Mbps STS-12/ STM-4 or 155.52 Mbps STS-3/STM-1 applications. The transceiver includes an on-chip Clock Multiplier Unit (CMU), which uses a high frequency PhaseLocked Loop (PLL) to generate the high-speed transmit serial clock from a slower external clock reference. It also provides Clock and Data Recovery (CDR) function by synchronizing its on-chip Voltage Controlled Oscillator (VCO) to the incoming serial data stream. The internal CDR unit can be disabled and bypassed in lieu of an externally recovered received clock from the optical module. Either the internally recovered clock or the externally recovered clock can be used for loop timing applications. The chip provides serial-to-parallel and parallel-to-serial converters using an 8-bit wide LVTTL system interface in both receive and transmit directions. The transmit section includes an option to accept a FIGURE 1. BLOCK DIAGRAM OF XRT91L31
parallel clock signal from the framer/mapper to synchronize the transmit section timing. The device can internally monitor Loss of Signal (LOS) condition and automatically mute received data upon LOS. An on-chip SONET/SDH frame byte and boundary detector and frame pulse generator offers the ability recover SONET/SDH framing and to byte align the receive serial data stream into the 8-bit parallel bus. APPLICATIONS
• SONET/SDH-based Transmission Systems • Add/Drop Multiplexers • Cross Connect Equipment • ATM and Multi-Service Switches, Routers and
Switch/Routers
• DSLAMS • SONET/SDH Test Equipment • DWDM Termination Equipment
STS-12/STM-4 or STS-3/STM-1 TRANSCEIVER
TXDI[7:0]
8
TXPCLK_IO REFCLKP/N TTLREFCLK
PISO (Parallel Input Serial Output)
ENB
Re-Timer
TXOP/N
MUX Div by 8
ENB
XOR
CMU DLOOP
RLOOPS
ALOOP
MUX
CDRAUXREFCLK
MUX
RXDO[7:0]
SIPO (Serial Input Parallel Output)
CDR MUX
RXIP/N
8
XRXCLKIP/N RXPCLKO Div by 8
Loop Filters
Control Block
Clock Control
CAP1N
CAP2N
CAP1P
CAP2P
DLOSDIS
LOSEXT
OOF FRAMEPULSE
CDRDIS
CMUFREQSEL
LOOPTIME
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
STS-12/STS-3
CDRREFSEL
PIO_CTRL
RLOOPS
DLOOP ALOOP
Reset
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER FEATURES
xr
REV. 1.0.2
• Targeted for SONET STS-12/STS-3 and SDH STM-4/STM-1 Applications • Selectable full duplex operation between STS-12/STM-4 standard rate of 622.08 Mbps or STS-3/STM-1
155.52 Mbps
• Single-chip fully integrated solution containing parallel-to-serial converter, clock multiplier unit (CMU), serialto-parallel converter, clock data recovery (CDR) functions, and a SONET/SDH frame and byte boundary detection circuit
• Ability to disable and bypass onchip CDR for external based received reference clock recovery thru
Differential LVPECL input pins XRXCLKIP/N
• 8-bit LVTTL parallel data bus paths running at 77.76 Mbps in STS-12/STM-4 or 19.44 Mbps in STS-3/STM-1
mode of operation
• Uses Differential LVPECL or Single-Ended LVTTL CMU reference clock frequencies of either 19.44 MHz or
77.76 MHz for both STS-12/STM-1 or STS-3/STM-1 operations
• Optional use of 77.76 MHz Single-Ended LVTTL input for independent CDR reference clock operation • Able to Detect and Recover SONET/SDH frame boundary and byte align received data on the parallel bus • Diagnostics features include LOS monitoring and automatic received data mute upon LOS • Provides Local, Remote and Split Loop-Back modes as well as Loop Timing mode • Optional flexibility to re-configure the transmit parallel bus clock output to a clock input and accept timing
signal from the framer/mapper device to permit the framer/mapper device time domain to be synchronized with the transceiver transmit timing.
• Meets Telcordia, ANSI and ITU-T G.783 and G.825 SDH jitter requirements including T1.105.03 - 2002
SONET Jitter Tolerance specification, Bellcore TR-NWT-000253 and GR-253-CORE, GR-253 ILR SONET Jitter specifications.
• Complies with ANSI/TIA/EIA-644 and IEEE P1596.3 3.3V LVDS standard, 3.3V LVPECL, and JESD 8-B
LVTTL and LVCMOS standard.
• Operates at 3.3V with 3.3V I/O • Less than 660mW in STS-3/STM-1 mode or 800mW in STS-12/STM-4 mode Typical Power Dissipation • Package: 10 x 10 x 2.0 mm 64-pin QFP
2
xr
REV. 1.0.2
XRT91L31 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
FIGURE 2. 64 QFP PIN OUT OF THE XRT91L31 (TOP VIEW)
AVDD PIO_CTRL GND VDD3.3 RRCLK_1 GND RRPOS_1 GND RRNEG_1 AGND_RX RCLKES AVDD3.3_RX NC CAP2P VDD CAP2N DS3/E3_2 CAP1N SDO CAP1P FSS AVDD3.3_TX RRNEG_2 AGND_TX RRPOS_2 TTLREFCLK RRCLK_2 GND GND VDD3.3 AVDD LOSEXT 49 50 49 51 50 52 51 53 52 54 53 55 54 56 55 57 56 58 57 59 58 60 59 60 61 61 62 62 63 63 64 64 48 48 47 47 46 46 45 45 44 44 43 43 42 42 41 41 40 40 39 39 38 38 37 37 36 36 35 35 34 34 33 33 32 3132 3031 2930 2829 2728 2627 2526 2425 2324 2223 2122 2021 1920 1819 1718 17
PART NUMBER XRT91L31IQ
RESET RESET LOOPTM_NOJA LOOPTIME CMUFREQSEL CMUFREQSEL VDD_PECL VDD_PECL TXOP TXOP TXON TXON LOSDDIS DLOSDIS EXTRXCLKIP XRXCLKIP EXTRXCLKIN XRXCLKIN VDD_PECL VDD_PECL OOF OOF CDRDIS CDRDIS RXIP RXIP RXIN RXIN VDD3.3 VDD/CDR_BW REFCLKP REFCLKP
1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16
AGND TXPCLK_IO FL1 TXDI7 STS1_1 TXDI6 MCLK_1 GND GND TXDI5 RCLK_1 TXDI4 RPOS_1 TXDI3 RNEG_1 TXDI2 VDD TXDI1 RNEG_0 TXDI0 RPOS_0 STS12/STS3 RCLK_0 CDRREFSEL GND VDD3.3 MCLK_0 DLOOP DJA_1/SDI RLOOPS AGND ALOOP
XRT91L30 XRT91L31
AGND FL_2 CDRAUXREFCLK STS1_2 VDD3.3 DJA_2/CS FRAMEPULSE MCLK_2 RXPCLKO GND GND RXDO7 RCLK_2 RXDO6 VDD RXDO5 RNEG_2 RXDO4 RPOS_2 RXDO3 GND RXDO2 DJA_0/SCLK GND DS3/E3_0 RXDO1 STS1_0 RXDO0 FL0 VDD3.3 AGND REFCLKN
ORDERING INFORMATION
PACKAGE 64 Pin Lead QFP OPERATING TEMPERATURE RANGE -40°C to +85°C
3
XRT91L31
REV. 1.0.2
xr
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................1
APPLICATIONS ...........................................................................................................................................1
FIGURE 1. BLOCK DIAGRAM OF XRT91L31 ...................................................................................................................................... 1 FEATURES ......................................................................................................................................................2 FIGURE 2. 64 QFP PIN OUT OF THE XRT91L31 (TOP VIEW)............................................................................................................ 3
ORDERING INFORMATION.....................................................................................................................3 TABLE OF CONTENTS ............................................................................................................ I
PIN DESCRIPTIONS ..........................................................................................................4
.....................................................................................................................................................................4 HARDWARE CONTROL ....................................................................................................................................4 TRANSMITTER SECTION ..................................................................................................................................7 RECEIVER SECTION ........................................................................................................................................9 POWER AND GROUND ..................................................................................................................................10 1.0 FUNCTIONAL DESCRIPTION .............................................................................................................12
1.1 STS-12/STM-4 AND STS-3/STM-1 MODE OF OPERATION ......................................................................... 12 1.2 CLOCK INPUT REFERENCE FOR CLOCK MULTIPLIER (SYNTHESIZER) UNIT ...................................... 12
TABLE 1: CMU REFERENCE FREQUENCY OPTIONS (DIFFERENTIAL OR SINGLE-ENDED) ................................................................... 12
1.3 DATA LATENCY ............................................................................................................................................. 12
TABLE 2: DATA INGRESS TO DATA EGRESS LATENCY ....................................................................................................................... 12
2.0 RECEIVE SECTION .............................................................................................................................13
2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 13
FIGURE 3. RECEIVE SERIAL INPUT INTERFACE BLOCK ..................................................................................................................... 13
2.2 RECIEVE SERIAL DATA INPUT TIMING ...................................................................................................... 14
FIGURE 4. RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING DIAGRAM .......................................................................................... 14 TABLE 3: RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING (STS-12/STM-4 OPERATION) ............................................................. 14 TABLE 4: RECEIVE HIGH-SPEED SERIAL DATA INPUT TIMING (STS-3/STM-1 OPERATION) ............................................................... 14
2.3 RECEIVE CLOCK AND DATA RECOVERY ...............................
