T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION

www.DataSheet4U.com XRT86VL3x T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION JULY 2006 REV. 1.2.0 GENERAL DESCRIPTION The XRT86VL3x is a 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology (Relayless, Reconfigurable, Redundancy) that comes in a 2-channel, 4-channel, or 8-channel package. The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86VL3x provides protection from power failures and hot swapping. The XRT86VL3x contains an integrated DS1/E1/J1 framer and LIU which provide DS1/E1/J1 framing and error accumulation in accordance with ANSI/ITU_T specifications. Each framer has its own framing synchronizer and transmit-receive slip buffers. The slip buffers can be independently enabled or disabled as required and can be configured to frame to the common DS1/E1/J1 signal formats. Each Framer block contains its own Transmit and Receive T1/E1/J1 Framing function. There are 3 Transmit HDLC controllers per channel which encapsulate contents of the Transmit HDLC buffers into LAPD Message frames. There are 3 Receive HDLC controllers per channel which extract the payload content of Receive LAPD Message frames from the incoming T1/E1/J1 data stream and write the contents into the Receive HDLC buffers. Each framer also contains a Transmit and Overhead Data Input port, which permits Data Link Terminal Equipment direct access to the outbound T1/E1/J1 frames. Likewise, a Receive Overhead output data port permits Data Link Terminal Equipment direct access to the Data Link bits of the inbound T1/E1/J1 frames. The XRT86VL3x fully meets all of the latest T1/E1/J1 specifications: ANSI T1/E1.107-1988, ANSI T1/ E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/ E1.408-1990, AT&T TR 62411 (12-90) TR54016, and ITU G-703, G.704, G706 and G.733, AT&T Pub. 43801, and ETS 300 011, 300 233, JT G.703, JT G.704, JT G706, I.431. Extensive test and diagnostic functions include Loop-backs, Boundary scan, Pseudo Random bit sequence (PRBS) test pattern generation, Performance Monitor, Bit Error Rate (BER) meter, forced error insertion, and LAPD unchannelized data payload processing according to ITU-T standard Q.921. Applications and Features (next page) FIGURE 1. XRT86VL3X N-CHANNEL DS1 (T1/E1/J1) FRAMER/LIU COMBO External Data Link Controller Local PCM Highway XRT86VL3x 1 of N-channels Tx Serial Data In Tx Overhead In Rx Overhead Out 1:2 Turns Ratio TTIP 2-Frame Slip Buffer Elastic Store Tx Framer Tx LIU Interface LLB LB TRING Tx Serial Clock ST-BUS Rx Serial Data Out Rx Serial Clock 2-Frame Slip Buffer Elastic Store RTIP 1:1 Turns Ratio Rx Framer Rx LIU Interface RRING PRBS Generator & Analyser Performance Monitor HDLC/LAPD Controllers LIU & Loopback Control RxLOS 8kHz sync OSC Signaling & Alarms JTAG DMA Interface Line Side Microprocessor Interface Back Plane 1.544-16.384 Mbit/s 3 4 System (Terminal) Side TxON Memory INT D[7:0] A[14:0] µP Select WR ALE_AS RD RDY_DTACK Intel/Motorola µP Configuration, Control & Status Monitor Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com XRT86VL3X T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION APPLICATIONS REV. 1.2.0 • 3 Integrated HDLC controllers per channel for transmit and receive, each controller having two 96-byte buffers (buffer 0 / buffer 1) • High-Density T1/E1/J1 interfaces for Multiplexers, Switches, LAN Routers and Digital Modems • SONET/SDH terminal or Add/Drop multiplexers (ADMs) • T1/E1/J1 add/drop multiplexers (MUX) • Channel Service Units (CSUs): T1/E1/J1 and Fractional T1/E1/J1 • HDLC Controllers Support SS7 • Timeslot assignable HDLC • V5.1 or V5.2 Interface • Automatic Performance Report Generation (PMON Status) can be inserted into the transmit LAPD interface every 1 second or for a single transmission • Digital Access Cross-connect System (DACs) • Digital Cross-connect Systems (DCS) • Frame Relay Switches and Access Devices (FRADS) • Alarm Indication Signal with Customer Installation signature (AIS-CI) • ISDN Primary Rate Interfaces (PRA) • PBXs and PCM channel bank • T3 channelized access concentrators and M13 MUX • Remote Alarm Indication with Customer Installation (RAI-CI) • Gapped Clock interface mode for Transmit and Receive. • Intel/Motorola and Power PC interfaces for configuration, control and status monitoring • Wireless base stations • ATM equipment with integrated DS1 interfaces • Multichannel DS1 Test Equipment • T1/E1/J1 Performance Monitoring • Voice over packet gateways • Routers FEATURES • Parallel search synchronization algorithm for fast frame • Wide choice of T1 framing structures: SF/D4, ESF, SLC®96, T1DM and N-Frame (non-signaling) • Direct access to D and E channels for fast transmission of data link information • PRBS, QRSS, and Network Loop Code generation and detection • Independent, full duplex DS1 Tx and Rx Framer/ LIUs • Two 512-bit (two-frame) elastic store, PCM frame slip buffers (FIFO) on TX and Rx provide up to 8.192 MHz asynchronous back plane connections with jitter and wander attenuation • Programmable Interrupt output pin • Supports programmed I/O and DMA modes of Read-Write access • Each framer block encodes and decodes the T1/ E1/J1 Frame serial data • Supports input PCM and signaling data at 1.544, 2.048, 4.096 and 8.192 Mbits. Also supports 4channel multiplexed 12.352/16.384 (HMVIP/H.100) Mbit/s on the back plane bus • Detects and forces Red (SAI), Yellow (RAI) and Blue (AIS) Alarms • Detects OOF, LOF, LOS errors and COFA conditions • Programmable output clocks for Fractional T1/E1/ J1 • Supports Channel Associated Signaling (CAS) • Supports Common Channel Signalling (CCS) • Supports ISDN Primary Rate Interface (ISDN PRI) signaling • Loopbacks: Local (LLB) and Line remote (LB) • Facilitates Inverse Multiplexing for ATM • Performance monitor with one second polling • Boundary scan (IEEE 1149.1) JTAG test port • Accepts external 8kHz Sync reference • 1.8V Inner Core Voltage • 3.3V I/O operation with 5V tolerant inputs • Extracts and inserts robbed bit signaling (RBS) 2 XRT86VL3X REV. 1.2.0 T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION ORDERING INFORMATION PART NUMBER XRT86VL38IB XRT86VL38IB484 XRT86VL34IB XRT86VL32IB PACKAGE 420 Tape Ball Grid Array 484 Shrink Thin Ball Grid Array 225 Plastic Ball Grid Array 225 Plastic Ball Grid Array OPERATING TEMPERATURE RANGE -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C 3 XRT86VL3X T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION REV. 1.2.0 LIST OF PARAGRAPHS 1.0 GENERAL DESCRIPTION AND INTERFACE .........................................................................................4 1.1 PHYSICAL INTERFACE ...................................................................................................................................... 4 1.2 R3 TECHNOLOGY (RELAYLESS / RECONFIGURABLE / REDUNDANCY) .................................................... 5 1.2.1 LINE CARD REDUNDANCY ........................................................................................................................................... 5 1.2.2 TYPICAL REDUNDANCY SCHEMES ............................................................................................................................ 5 1.2.3 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS ........................................................................................................ 5 1.2.4 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY ...................................................................................... 5 1.2.5 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY ......................................................................................... 6 1.3 POWER FAILURE PROTECTION ....................................................................................................................... 7 1.4 OVERVOLTAGE AND OVERCURRENT PROTECTION .................................................................................... 7 1.5 NON-INTRUSIVE MONITORING ......................................................................................................................... 7 1.6 T1/E1 SERIAL PCM INTERFACE ....................................................................................................................... 8 1.7 T1/E1 FRACTIONAL INTERFACE ...................................................................................................................... 9 1.8 T1/E1 TIME SLOT SUBSTITUTION AND CONTROL ....................................................................................... 10 1.9 ROBBED BIT SIGNALING/CAS SIGNALING ................................................................................................... 11 1.10 OVERHEAD INTERFACE ................................................................................................................................ 12 1.11 FRAMER BYPASS MODE ............................................................................................................................... 14 1.12 HIGH-SPEED NON-MULTIPLEXED INTERFACE .......................................................................................... 15 1.13 HIGH-SPEED MULTIPLEXED INTERFACE ................................................................................................... 16 2.0 LOOPBACK MODES OF OPERATION .................................................................................................17 2.1 LIU PHYSICAL INTERFACE LOOPBACK DIAGNOSTICS .............................................................................. 17 2.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................... 17 2.1.2 REMOTE LOOPBACK ...............