OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

www.DataSheet4U.com PRELIMINARY JULY 2006 XRT86VL38 REV. P1.0.9 OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION GENERAL DESCRIPTION The XRT86VL38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology (Relayless, Reconfigurable, Redundancy). The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86VL38 provides protection from power failures and hot swapping. The XRT86VL38 contains an integrated DS1/E1/J1 framer and LIU which provide DS1/E1/J1 framing and error accumulation in accordance with ANSI/ITU_T specifications. Each framer has its own framing synchronizer and transmit-receive slip buffers. The slip buffers can be independently enabled or disabled as required and can be configured to frame to the common DS1/E1/J1 signal formats. Each Framer block contains its own Transmit and Receive E1/J1 Framing function. There are 3 Transmit HDLC controllers per channel which encapsulate contents of the Transmit HDLC buffers into LAPD Message frames. There are 3 Receive HDLC controllers per channel which extract the payload content of Receive LAPD Message frames from the incoming E1/J1 data stream and write the contents into the Receive HDLC buffers. Each framer also contains a Transmit and Overhead Data Input port, which permits Data Link Terminal Equipment direct access to the outbound E1/J1 frames. Likewise, a Receive Overhead output data port permits Data Link Terminal Equipment direct access to the Data Link bits of the inbound E1/J1 frames. The XRT86VL38 fully meets all of the latest E1/J1 specifications: ANSI E1.107-1988, ANSI E1.4031995, ANSI E1.231-1993, ANSI E1.408-1990, AT&T TR 62411 (12-90) TR54016, and ITU G-703, G.704, G706 and G.733, AT&T Pub. 43801, and ETS 300 011, 300 233, JT G.703, JT G.704, JT G706, I.431. Extensive test and diagnostic functions include Loopbacks, Boundary scan, Pseudo Random bit sequence (PRBS) test pattern generation, Performance Monitor, Bit Error Rate (BER) meter, forced error insertion, and LAPD unchannelized data payload processing according to ITU-T standard Q.921. Applications and Features (next page) FIGURE 1. XRT86VL38 8-CHANNEL DS1 (E1/J1) FRAMER/LIU COMBO External Data Link Controller Local PCM Highway XRT86VL38 1 of 8-channels Tx Serial Data In Tx Overhead In Rx Overhead Out 1:2 Turns Ratio TTIP 2-Frame Slip Buffer Elastic Store Tx Framer Tx LIU Interface LLB LB TRING Tx Serial Clock ST-BUS Rx Serial Data Out Rx Serial Clock 2-Frame Slip Buffer Elastic Store RTIP 1:1 Turns Ratio Rx Framer Rx LIU Interface RRING PRBS Generator & Analyser Performance Monitor HDLC/LAPD Controllers LIU & Loopback Control RxLOS 8kHz sync OSC Signaling & Alarms JTAG DMA Interface Line Side Microprocessor Interface Back Plane 1.544-16.384 Mbit/s 3 System (Terminal) Side TxON Memory INT D[7:0] µP A[14:0] Select 4 WR ALE_AS RD RDY_DTACK Intel/Motorola µP Configuration, Control & Status Monitor Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com XRT86VL38 APPLICATIONS PRELIMINARY REV. P1.0.9 OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION • High-Density E1/J1 interfaces for Multiplexers, Switches, LAN Routers and Digital Modems • SONET/SDH terminal or Add/Drop multiplexers (ADMs) • E1/J1 add/drop multiplexers (MUX) • Channel Service Units (CSUs): E1/J1 and Fractional E1/J1 • Digital Access Cross-connect System (DACs) • Digital Cross-connect Systems (DCS) • Frame Relay Switches and Access Devices (FRADS) • ISDN Primary Rate Interfaces (PRA) • PBXs and PCM channel bank • T3 channelized access concentrators and M13 MUX • Wireless base stations • ATM equipment with integrated DS1 interfaces • Multichannel DS1 Test Equipment • E1/J1 Performance Monitoring • Voice over packet gateways • Routers FEATURES • Eight independent, full duplex DS1 Tx and Rx Framer/LIUs • Two 512-bit (two-frame) elastic store, PCM frame slip buffers (FIFO) on TX and Rx provide up to 8.192 MHz asynchronous back plane connections with jitter and wander attenuation • Supports input PCM and signaling data at 1.544, 2.048, 4.096 and 8.192 Mbits. Also supports 4-channel multiplexed 12.352/16.384 (HMVIP/H.100) Mbit/s on the back plane bus • Programmable output clocks for Fractional E1/J1 • Supports Channel Associated Signaling (CAS) • Supports Common Channel Signalling (CCS) • Supports ISDN Primary Rate Interface (ISDN PRI) signaling • Extracts and inserts robbed bit signaling (RBS) • 3 Integrated HDLC controllers per channel for transmit and receive, each controller having two 96-byte buffers (buffer 0 / buffer 1) • HDLC Controllers Support SS7 • Timeslot assignable HDLC • V5.1 or V5.2 Interface • Automatic Performance Report Generation (PMON Status) can be inserted into the transmit LAPD interface every 1 second or for a single transmission • Alarm Indication Signal with Customer Installation signature (AIS-CI) • Remote Alarm Indication with Customer Installation (RAI-CI) • Gapped Clock interface mode for Transmit and Receive. 2 PRELIMINARY REV. P1.0.9 XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION • Intel/Motorola and Power PC interfaces for configuration, control and status monitoring • Parallel search algorithm for fast frame synchronization • Wide choice of T1 framing structures: SF/D4, ESF, SLC®96, T1DM and N-Frame (non-signaling) • Direct access to D and E channels for fast transmission of data link information • PRBS, QRSS, and Network Loop Code generation and detection • Programmable Interrupt output pin • Supports programmed I/O and DMA modes of Read-Write access • Each framer block encodes and decodes the E1/J1 Frame serial data • Detects and forces Red (SAI), Yellow (RAI) and Blue (AIS) Alarms • Detects OOF, LOF, LOS errors and COFA conditions • Loopbacks: Local (LLB) and Line remote (LB) • Facilitates Inverse Multiplexing for ATM • Performance monitor with one second polling • Boundary scan (IEEE 1149.1) JTAG test port • Accepts external 8kHz Sync reference • 1.8V Inner Core Voltage • 3.3V I/O operation with 5V tolerant inputs • 420-pin PBGA package or 484-pin STBGA package with -40°C to +85°C operation ORDERING INFORMATION PART NUMBER XRT86VL38IB XRT86VL38IB484 PACKAGE 420 Plastic Ball Grid Array 484 Shrink Thin Ball Grid Array OPERATING TEMPERATURE RANGE -40°C to +85°C -40°C to +85°C 3 XRT86VL38 PRELIMINARY REV. P1.0.9 OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION 420 BALL - PLASTIC BALL GRID ARRAY (BOTTOM VIEW, SEE PIN LIST FOR DESCRIPTION) 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF OOOOOOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOOOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOOOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOOOOOO 4 PRELIMINARY REV. P1.0.9 XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION 484 BALL - SHRINK THIN BALL GRID ARRAY (BOTTOM VIEW - SEE PIN LIST FOR DESCRIPTION) 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB OOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOO 5 XRT86VL38 PRELIMINARY REV. P1.0.9 OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION LIST OF PARAGRAPHS 1.0 REGISTER DESCRIPTIONS - E1 MODE ..............................................................................................12 2.0 LINE INTERFACE UNIT (LIU SECTION) REGISTERS .......................................................................148 I PRELIMINARY REV. P1.0.9 XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION LIST OF FIGURES Figure 1.: XRT86VL38 8-channel DS1 (E1/J1) Framer/LIU Combo .................................................................................. 1 II XRT86VL38 PRELIMINARY REV. P1.0.9 OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION LIST OF TABLES Table 1:: Register Summary .............................................................................................................................................. 6 Table 2:: Clock Select Register (CSR) Hex Address: 0xn100 .................. 12 Table 3:: Line Interface Control Register (LICR) Hex Address: 0xn101 .................... 14 Table 4:: General Purpose Input/Output 0 Control Register (GPIOCR0) Hex Address: 0x0102 ...................... 16 Table 5:: General Purpose Input/Output 1 Control Register (GPIOCR1) Hex Address: 0x4102 ....................... 17 Table 6:: Framing Select Register (FSR) Hex Address: 0xn107 ................ 18 Table 7:: Alarm Generation Register (AGR) Hex Address: 0xn108 ................... 22 Table 8:: Synchronization MUX Register (SMR) Hex Address: 0xn109 ................. 24 Table 9:: Transmit Signaling and Data Link Select Register (TSDLSR) Hex Address:0xn10A .................... 27 Table 10:: Framing Control Register (FCR) Hex Address: 0xn10B ............... 30 Table 11:: Receive Signaling & Data Link Select Register (RSDLSR) Hex Address: 0xn10C ................