QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

www.DataSheet4U.com xr JULY 2005 PRELIMINARY XRT86VL34 REV. P1.0.5 QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION GENERAL DESCRIPTION The XRT86VL34 is a four-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology (Relayless, Reconfigurable, Redundancy). The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86VL34 provides protection from power failures and hot swapping. The XRT86VL34 contains an integrated DS1/E1/J1 framer and LIU which provide DS1/E1/J1 framing and error accumulation in accordance with ANSI/ITU_T specifications. Each framer has its own framing synchronizer and transmit-receive slip buffers. The slip buffers can be independently enabled or disabled as required and can be configured to frame to the common DS1/E1/J1 signal formats. Each Framer block contains its own Transmit and Receive T1/E1/J1 Framing function. There are 3 Transmit HDLC controllers per channel which encapsulate contents of the Transmit HDLC buffers into LAPD Message frames. There are 3 Receive HDLC controllers per channel which extract the payload content of Receive LAPD Message frames from the incoming T1/E1/J1 data stream and write the contents into the Receive HDLC buffers. Each framer also contains a Transmit and Overhead Data Input port, which permits Data Link Terminal Equipment direct access to the outbound T1/E1/J1 frames. Likewise, a Receive Overhead output data port permits Data Link Terminal Equipment direct access to the Data Link bits of the inbound T1/E1/J1 frames. The XRT86VL34 fully meets all of the latest T1/E1/J1 specifications: ANSI T1/E1.107-1988, ANSI T1/ E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/ E1.408-1990, AT&T TR 62411 (12-90) TR54016, and ITU G-703, G.704, G706 and G.733, AT&T Pub. 43801, and ETS 300 011, 300 233, JT G.703, JT G.704, JT G706, I.431. Extensive test and diagnostic functions include Loop-backs, Boundary scan, Pseudo Random bit sequence (PRBS) test pattern generation, Performance Monitor, Bit Error Rate (BER) meter, forced error insertion, and LAPD unchannelized data payload processing according to ITU-T standard Q.921. Applications and Features (next page) FIGURE 1. XRT86VL34 4-CHANNEL DS1 (T1/E1/J1) FRAMER/LIU COMBO External Data Link Controller Local PCM Highway XRT86VL34 1 of 4-channels Tx Serial Data In Tx Overhead In Rx Overhead Out 1:2 Turns Ratio TTIP 2-Frame Slip Buffer Elastic Store Tx Framer Tx LIU Interface LLB LB TRING Tx Serial Clock ST-BUS Rx Serial Data Out Rx Serial Clock 2-Frame Slip Buffer Elastic Store RTIP 1:1 Turns Ratio Rx Framer Rx LIU Interface RRING PRBS Generator & Analyser Performance Monitor HDLC/LAPD Controllers LIU & Loopback Control RxLOS 8kHz sync OSC Signaling & Alarms JTAG DMA Interface Line Side Microprocessor Interface Back Plane 1.544-16.384 Mbit/s 3 System (Terminal) Side TxON Memory INT D[7:0] µP A[13:0] Select 4 WR ALE_AS RD RDY_DTACK Intel/Motorola µP Configuration, Control & Status Monitor Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com XRT86VL34 REV. P1.0.5 PRELIMINARY xr QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION APPLICATIONS • High-Density T1/E1/J1 interfaces for Multiplexers, Switches, LAN Routers and Digital Modems • SONET/SDH terminal or Add/Drop multiplexers (ADMs) • T1/E1/J1 add/drop multiplexers (MUX) • Channel Service Units (CSUs): T1/E1/J1 and Fractional T1/E1/J1 • Digital Access Cross-connect System (DACs) • Digital Cross-connect Systems (DCS) • Frame Relay Switches and Access Devices (FRADS) • ISDN Primary Rate Interfaces (PRA) • PBXs and PCM channel bank • T3 channelized access concentrators and M13 MUX • Wireless base stations • ATM equipment with integrated DS1 interfaces • Multichannel DS1 Test Equipment • T1/E1/J1 Performance Monitoring • Voice over packet gateways • Routers FEATURES • Four independent, full duplex DS1 Tx and Rx Framer/LIUs • Two 512-bit (two-frame) elastic store, PCM frame slip buffers (FIFO) on TX and Rx provide up to 8.192 MHz asynchronous back plane connections with jitter and wander attenuation • Supports input PCM and signaling data at 1.544, 2.048, 4.096 and 8.192 Mbits. Also supports 4-channel multiplexed 12.352/16.384 (HMVIP/H.100) Mbit/s on the back plane bus • Programmable output clocks for Fractional T1/E1/J1 • Supports Channel Associated Signaling (CAS) • Supports Common Channel Signalling (CCS) • Supports ISDN Primary Rate Interface (ISDN PRI) signaling • Extracts and inserts robbed bit signaling (RBS) • 3 Integrated HDLC controllers per channel for transmit and receive, each controller having two 96-byte buffers (buffer 0 / buffer 1) • HDLC Controllers Support SS7 • Timeslot assignable HDLC • V5.1 or V5.2 Interface • Automatic Performance Report Generation (PMON Status) can be inserted into the transmit LAPD interface every 1 second or for a single transmission • Alarm Indication Signal with Customer Installation signature (AIS-CI) • Remote Alarm Indication with Customer Installation (RAI-CI) • Gapped Clock interface mode for Transmit and Receive. • Intel/Motorola and Power PC interfaces for configuration, control and status monitoring • Parallel search algorithm for fast frame synchronization • Wide choice of T1 framing structures: SF/D4, ESF, SLC®96, T1DM and N-Frame (non-signaling) • Direct access to D and E channels for fast transmission of data link information 2 xr PRELIMINARY XRT86VL34 REV. P1.0.5 QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION • PRBS, QRSS, and Network Loop Code generation and detection • Programmable Interrupt output pin • Supports programmed I/O and DMA modes of Read-Write access • Each framer block encodes and decodes the T1/E1/J1 Frame serial data • Detects and forces Red (SAI), Yellow (RAI) and Blue (AIS) Alarms • Detects OOF, LOF, LOS errors and COFA conditions • Loopbacks: Local (LLB) and Line remote (LB) • Facilitates Inverse Multiplexing for ATM • Performance monitor with one second polling • Boundary scan (IEEE 1149.1) JTAG test port • Accepts external 8kHz Sync reference • 1.8V Inner Core • 3.3V CMOS operation with 5V tolerant inputs • 225-pin PBGA package with -40°C to +85°C operation ORDERING INFORMATION PART NUMBER XRT86VL34IB PACKAGE 225 Plastic Ball Grid Array OPERATING TEMPERATURE RANGE -40°C to +85°C 3 XRT86VL34 PRELIMINARY QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION xr REV. P1.0.5 LIST OF PARAGRAPHS 1.0 REGISTER DESCRIPTIONS - E1 MODE ................................................................................................9 2.0 LINE INTERFACE UNIT (LIU SECTION) REGISTERS .......................................................................143 I xr REV. P1.0.5 PRELIMINARY XRT86VL34 QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION LIST OF FIGURES Figure 1.: XRT86VL34 4-channel DS1 (T1/E1/J1) Framer/LIU Combo ............................................................................. 1 II xr PRELIMINARY XRT86VL34 REV. P1.0.5 QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION TABLE 1: REGISTER SUMMARY......................................................................................................................................................... 4 TABLE 2: CLOCK SELECT REGISTER (CSR) HEX ADDRESS: 0XN100 .......................... 9 TABLE 3: LINE INTERFACE CONTROL REGISTER (LICR) HEX ADDRESS: 0XN101........................ 11 TABLE 4: FRAMING SELECT REGISTER (FSR) HEX ADDRESS: 0XN107 ....................... 13 TABLE 5: ALARM GENERATION REGISTER (AGR) HEX ADDRESS: 0XN108 ......................... 17 TABLE 6: SYNCHRONIZATION MUX REGISTER (SMR) HEX ADDRESS: 0XN109 ....................... 19 TABLE 7: TRANSMIT SIGNALING AND DATA LINK SELECT REGISTER (TSDLSR) HEX ADDRESS:0XN10A ........................ 21 TABLE 8: FRAMING CONTROL REGISTER (FCR) HEX ADDRESS: 0XN10B....................... 24 TABLE 9: RECEIVE SIGNALING & DATA LINK SELECT REGISTER (RSDLSR) HEX ADDRESS: 0XN10C ....................... 26 TABLE 10: RECEIVE SIGNALING CHANGE REGISTER 0 (RSCR 0) HEX ADDRESS: 0XN10D................... 28 TABLE 11: RECEIVE SIGNALING CHANGE REGISTER 1 (RSCR 1) HEX ADDRESS: 0XN10E .................. 28 TABLE 12: RECEIVE SIGNALING CHANGE REGISTER 2 (RSCR 2) HEX ADDRESS: 0XN10F .................. 28 TABLE 13: RECEIVE SIGNALING CHANGE REGISTER 3 (RSCR 3) HEX ADDRESS: 0XN110 ................. 29 TABLE 14: RECEIVE NATIONAL BITS REGISTER (RNBR) HEX ADDRESS: 0XN111...................... 30 TABLE 15: RECEIVE EXTRA BITS REGISTER (REBR) HEX ADDRESS: 0XN112..................... 31 TABLE 16: DATA LINK CONTROL REGISTER (DLCR1) HEX ADDRESS: 0XN113 ....................... 33 TABLE 17: TRANSMIT DATA LINK BYTE COUNT REGISTER (TDLBCR1) HEX ADDRESS: 0XN114 .................... 35 TABLE 18: RECEIVE DATA LINK BYTE COUNT REGISTER (RDLBCR1) HEX ADDRESS: 0XN115 ...................... 36 TABLE 19: SLIP BUFFER CONTROL REGISTER (SBCR) HEX ADDRESS: 0XN116 ..................... 37 TABLE 20: FIFO LATENCY REGISTER (FFOLR) HEX ADDRESS: 0XN117 ....................... 38 TABLE 21: DMA 0 (WRITE) CONFIGURATION REGISTER (D0WCR) HEX ADDRESS: 0XN118...................... 39 TABLE 22: DMA 1 (READ) CONFIGURATION REGISTER (D1RCR) HEX ADDRESS: 0XN119...................... 40 TABLE 23: INTERRUPT CONTROL REGISTER (ICR) HEX ADDRESS: 0XN11A ..................... 41 TABLE 24: LAPD SELECT REGISTER (LAPDSR) HEX ADDRESS: 0XN11B ....................... 42 TABLE 25: PERFORMANCE REPORT CONTROL REGISTER (PRCR) HEX ADDRESS: 0XN11D ..................... 42 TABLE 26: GAPPED CLOCK CONTROL REGISTER (GCCR) HEX ADDRESS: 0XN11E ...................... 43 TABLE 27: TRANSMIT INTERFACE CONTROL REGISTER (TICR) HEX ADDRESS:0XN120 ..................... 44 TABLE 28: TRANSMIT INTERFACE SPEED WHEN MULTIPLEXED MODE IS DISABLED (TXMUXEN =