VT/TU MAPPER AND M13 MULTIPLEXER

www.DataSheet4U.com Datasheet, P1.0.1, September 2005 INTEGRATED 28-CHANNEL T1/E1 LIU/FRAMER, VT/TU MAPPER AND M13 MULTIPLEXER XRT86SH328 Network & Transmission Products XRT86SH328 Datasheet GENERAL DESCRIPTION 1 GENERAL DESCRIPTION The XRT86SH328 is an integrated VT/TU Mapper with 28 port T1/E1 Line Interface Units. The XRT86SH328 contains integrated DS1/E1/J1 Framers for performance monitoring. The XRT86SH328 processes the Section, Line and Path overhead in the SONET/SDH data-stream. The processing of path overhead bytes within the STS-1s or TUG-3s include 64 bytes (of buffer) for storing the (Section Trace and Path Trace) messages. Path Overhead bytes can be accessed either by on-chip registers or a Serial Output Port. Each of the 28 T1 or E1 Channels use an internal DeSynchronizer circuit with an internal pointer leak algorithm. This removes the jitter due to mapping and pointer adjustments from the T1 or E1 signals that are de-mapped from the incoming SONET/SDH datastream. These De-Synchronizer circuits do not need any external clock references for its operation. The Transmit Blocks permit flexible insertion of TOH and POH bytes via both Hardware and Software control. The Receive Blocks receive a SONET STS-1 signals or an SDH STM-1 signal and performs the necessary Transport and Path Overhead Processing. A PRBS Pattern Generator and Receiver is implemented within each of the 28 T1/E1 channels in order to implement and measure Bit-Error performance. A general purpose Microprocessor Interface is included for control, configuration and monitoring. 1.1 FEATURES • Provides mapping of up to 28 T1 streams as Asynchronous VT1.5 into an STS-1 SPE or TU-11 tributary unit into an STM-1/VC-3 or TUG-3 from STM1/VC-4 • Supports 28 T1 streams M13 multiplexed into a serial DS3 • Supports 21 E1 streams M13 multiplexed into a serial DS3 (compliant with ITU-T G.747) • 28 T1 Streams M13 Multiplexed into a DS3 and DS3 is asynchronously mapped into STS-1. 1.2 APPLICATIONS • 21 E1 Streams M13 Multiplexed into a DS3 (ITU-T • Channelized and Unchannelized DS3 applications G.747) and DS3 is asynchronously mapped into STS• T1/E1 Terminals 1. • SONET/SDH ADM Table 1 Ordering Information Product Number XRT86SH328IB Package Type 568 Ball BGA Operating Temperature Range -25°C to +85°C • Supports 21 E1 mapped as Asynchronous VT2 into an STS-1 SPE or TU-12 tributary units into STM-1/VC-3 or TUG-3 from a STM-1/VC-4. • Supports TU cross-mapping function TU-12/VC-11/ T1. • Supports mixed mapping of VT-G/VT1.5 and VT-G/ VT2. • Supports mixed mapping of TUG-2/TU-11 and TUG-2/ TU-12 • 28 VT1.5/TU-11 or 21 VT-2/TU-12 tributaries can be passed as transparent between SONET/SDH Telecom Bus on the line side and Clock and Data on the system side. • Supports Unframed T1/E1 signals • Supports DS1/E1 Performance Monitoring in both Egress and Ingress direction • VC-11/VC-12 Tandem Connection Monitoring support • Complies with the Category I Intrinsic Jitter Requirements for DS1 signals being de-mapped from SONET, per Telcordia GR-253-CORE • Complies with the "Mapping Jitter Generation Specification" for DS1 and E1 signals being demapped from SDH, per ITU-T G.783 • Complies with the "Combined Jitter Generation Specification" for DS1 and E1 signals being demapped from SDH, per ITU-T G.783 • Line and Facility Loop-backs • Each of the 28 T1/E1 Channels includes a PRBS Generator and Receiver. • Each of the 28 VT-Mapper blocks are capable of generating BIP-2 and REI errors upon software command (for diagnostic purposes). • ·The Transmit and Receive DS3 Framer blocks support both the M13(M23) and the C-bit Parity Framing formats. • Integrated 28 T1/E1/J1 Short-Haul Line Interface Units • IEEE 1149.1 Standard Boundary Scan • Low Power: 1.8V Power Supply for Core Logic; 3.3V Power Supply for I/O • General Purpose Microprocessor Interface Datasheet 2 P1.0.1, September 1, 2005 Datasheet Figure 1 Microprocessor Interface STM1/ STS-1 Telecom Bus Interface STS-1 to VT1.5/2.0 TUG2/3 to VC11/12 Mux 28VT1.5/ VC11,21VT2.0/ VC12 Overhead Termination STS-1 To DS3/E3 Mapper/ DeMapper Pointer Justify Jitter Attenuator/ DeSynchronizer Block Diagram of the XRT86SH328 3 DS3/E3 Framer M13/E13 Mux/ DeMux DS1/VT1.5,E1/VT2.0,DS1/ VC11 and E1/VC12 Mapper/DeMapper DS1/E1 Framers 28 T1/E1/ J1 LIU DS3/E3 Serial I/F Boundry Scan GENERAL DESCRIPTION P1.0.1, September 1, 2005 XRT86SH328 Datasheet XRT86SH328 Datasheet Table of Contents Page XRT86SH328 Table of Contents 1 GENERAL DESCRIPTION ................................................................................................................................................................. 2 1.1 FEATURES ......................................................................................................................................................................................... 2 1.2 APPLICATIONS .................................................................................................................................................................................. 2 XRT86SH328 Table of Contents ............................................................................................................................................................................I XRT86SH328List of Figures ..................................................................................................................................................................................i XRT86SH328 List of Tables ..................................................................................................................................................................................a 2 XRT86SH328 PIN DESCRIPTIONS ................................................................................................................................................... 4 Datasheet I P1.0.1, September 1, 2005 XRT86SH328 Datasheet List of Figures Page XRT86SH328List of Figures Figure 1 Block Diagram of the XRT86SH328 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Datasheet i P1.0.1, September 1, 2005 XRT86SH328 Datasheet List of Tables Page XRT86SH328 List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Microprocessor Interface - Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Boundary Scan and other Test Pins - Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Low-Speed Side Interface - T1/E1 Line Signals - Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Low-Speed Side Interface - System-Side Signals- Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Miscellaneous Timing/Clock Signals - Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Power and Ground - Pin Descxriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Datasheet a P1.0.1, September 1, 2005 XRT86SH328 Datasheet XRT86SH328 PIN DESCRIPTIONS 2 Table 2 Pin/Ball Number AA30 V27 W29 W30 V29 U28 U29 T27 T29 R28 R27 R30 P29 N29 N28 M30 M29 L30 U26 U27 T26 T30 R29 P27 P26 N27 XRT86SH328 PIN DESCRIPTIONS Microprocessor Interface - Pin Descriptions Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 D0 D1 D2 D3 D4 D5 D6 D7 I/O Bi-Directional Data Bus pins (Microprocessor Interface): These pins are used to drive and receive data over the bi-directional data bus, whenever the Microprocessor performs READ or WRITE operations with the Microprocessor Interface of the XRT86SH328. Type I Description Address Bus Input pins (Microprocessor Interface): These pins permit the Microprocessor to identify on-chip registers and Buffer/Memory locations (within the XRT86SH328) whenever it performs READ and WRITE operations with the XRT86SH328. Datasheet 4 P1.0.1, September 1, 2005 XRT86SH328 Datasheet XRT86SH328 PIN DESCRIPTIONS Table 2 Pin/Ball Number V30 Microprocessor Interface - Pin Descriptions Pin Name ALE/AS Type I Description Address Latch Enable/Address Strobe: The function of this input pin depends upon which mode the Microprocessor Interface has been configured to operate in. Intel-Asynchronous Mode - ALE If the Microprocessor Interface of the XRT86SH328 has been configured to operate in the Intel-Asynchronous Mode, then this active-high input pin is used to latch the address (present at the Microprocessor Interface Address Bus pins (A[17:0]) into the XRT86SH328 Microprocessor Interface block and to indicate the start of a READ or WRITE cycle. Pulling this input pin "High" enables the input bus driver s for the Address Bus input pins (A[17:0]). The contents of the Address Bus will be latched into the XRT86SH328 Microprocessor Interface circuitry, upon the falling edge of this input signal. Motorola-Asynchronous (68K) Mode - AS* If the Microprocessor Interface has been configured to operate in the MotorolaAsynchronous Mode, then this active-low input pin is used to latch the data (residing on the Address Bus, A[17:0]) into the Microprocessor Interfac