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MAY 2007
PRELIMINARY
XRT86SH221
REV. P1.0.5
SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU
GENERAL DESCRIPTION
The XRT86SH221 (Voyager-Lite) is a physical layer SDH to PDH mapper/demapper which enables E1 aggregation to STM-1 via standard VC-12 to AU-3 and TUG-3/AU-4 mapping protocols. Voyager-Lite supports all the framing, mapping and grooming functions required for STM-1 mapper applications. The device generates and terminates all SDH Regenerator Section, Multiplexer Section and Path Overhead including the low-order Virtual Container (VC) Path Overhead. E1 framing is transparent; therefore, the device neither generates nor terminates the E1 frame. FIGURE 1. SIMPLIFIED BLOCK DIAGRAM
SDH OH Drop VC-4 POH Drop
A single Voyager-Lite performs mapping of 21 asynchronous E1 spans to either VC-12/TU-12/TUG2/ VC-3/AU-3/STM-0 or VC-12/TU-12/TUG-2/TUG-3/ STM-0. Mapping to STM-1 requires (3) Voyager-Lite devices with one acting as "master" framer and two acting as "slave" framers. In this configuration, Voyager-Lite performs all the necessary framing, pointer processing and mapping functions required for mapping of 63xE1 spans to either VC-12/TU-12/ TUG-2/VC-3/AU-3/STM-1 or VC-12/TU-12/TUG-2/ TUG-3/VC-4/AU-4/STM-1 as shown in the block diagram.
19.44Mhz
8kHz
STM-1 SOH Processor
Master Slave
XRT86SH221 Voyager Lite
Telecom Bus Rx Telecom Bus or Serial Port Interface Telecom Bus Tx
SDH TransPort Proc (SOH) Rx
SDH Path Proc (POH) TU-12 To TUG2 Rx
VC-12 Mapper + TU-12 Pointer Proc Rx
VC-12 Cross Connect 21x21 Rx
21 Ch E1 Frame Sync Bit Retimer
21 Ch E1 Short Haul LIU Tx
Egress
SDH TransPort Proc (SOH) Tx
VC3/ AU3 TUG3/ VC4/ AU4 Tx
VC-12 Mapper + TU-12 Pointer Proc Tx
VC-12 Cross Connect 21x21 Tx
21 Ch E1 Short Haul LIU Rx
Ingress Recovered Line Clock
STM-1 SOH Processor
PLL E1, 2xE1 4xE1, 8xE1
JTAG
Microprocessor
SDH OH Add
VC-4 P OHSingle Input Clock Add Reference
JTAG Port
Microprocessor Interface
PACKAGE ORDERING INFORMATION
PRODUCT NUMBER XRT86SH221IB PACKAGE TYPE 388 PBGA OPERATING TEMPERATURE RANGE -40° to +85° C C
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRT86SH221 FEATURES
VT Mapper
PRELIMINARY
REV. P1.0.5
SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU
• Maps up to 21 synchronous or asynchronous E1 signals to SDH AU-3 via TUG-2 and TU-12, or to SDH
STM-0 payload capacity via VT Groups and VT2.
• Dynamic VT/TU size selection. • Inserts valid V5 bit interleaved parity BIP-2 in the transmit direction. • Detects and counts V5 BIP-2 errors for performance monitoring. • Configurable remote error indication REI-V insertion for V5 BIP-2 errors. • Supports proprietary V5 remote loopcodes. • Detects and counts remote errors. • Automatic receive monitor functions include VT/TU remote defect indication RDI-V, VT/TU remote failure
indication RFI-V, VT/TU remote error indication REI-V, BIP-2 errors, VT/TU AIS, VT/TU Automatic Protection Switching (APS) signalling for low order path level, and VT/TU loss of pointer LOP-V.
• Automatic receive monitoring functions can be configured to provide an interrupt to the control system, or the
device can be operated in a polled mode.
• Test pattern generation and detection/dropping for setup and maintenance. • User configurable for VT/TU label, AIS-V, RDI-V, RFI-V, REI-V, APS, force BIP-2 errors, or unequipped
tributary insertion. E1 Receive Framing Synchronizer
• Provides a standard compliant 2.048 Mbits PCM30 CRC-4 E1 framer. • Provides off-line framer. • Complies with standards such as: ITU-T G.703, G.704, G.706 (including Annex B), G.732, G.735, G.736,
G.737, G.761, G.823, I.431 and ETS 300 011, 300 233.
• Supports FAS, Signaling Multiframe, and CRC-4 framing structure. • FAS reframe time is 625µs maximum. • Provides Loss Of Frame (LOF), Loss of Multiframe detection. • Provides Change Of Frame Alignment (COFA) detection. • Provides Change Of signaling MultiFrame Alignment (COMFA) detection. • Provides a 2-frame slip buffer for bit retiming.
2
PRELIMINARY
REV. P1.0.5
XRT86SH221
SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU
SDH Transmitter
• Performs standard STM-0/STM-1 transmit processing. • Conforms to ITU-T I.432, ANSI T1.105, and Bellcore-253 • Provides a 51.84MHz STM-0 serial interface or 6MHz / 19MHz 8-bit STM-0 / STM-1 parallel interface. • Performs SDH frame insertion and accepts external frame synchronization. • Performs optional transmit data scrambling. • Performs POH, SDH OH generation/insertion. • Generates transmit payload pointer (H1, H2) (fixed at 522) with NDF insertion. • Inserts A1/A2 with optional error mask. • Computes and inserts BIP-8 (B1, B2) with optional error mask. • Generates AIS-L, REI-L and RDI-L according to receiver state with option of SW or HW insertion. • Inserts LOS, forces SEF by software. • Generates RDI-P and REI-P automatically with optional SW or HW override. • Inserts fixed-stuff columns, calculates and inserts B3 error code.
SDH Receiver
• Performs standard STM-0/STM-1 receive processing. • Conforms to ITU-T I.432, ANSI T1.105, and Bellcore-253. • Provides fully programmable threshold detection for SD and SF conditions. • Provides a 51.84MHz STM-0 serial interface or 6MHz / 19MHz 8-bit STM-0 / STM-1 parallel interface. • Provides section trace buffer with mismatch detection and invalid message detection. • Performs SDH frame synchronization. • Supports NDF, positive stuff and negative stuff for pointer processor. • Performs receive data de-scrambling. • Performs POH, SDH OH interpretation/extraction. • Interprets payload pointer (H1, H2). • Detects Out Of Frame (OOF), Loss Of Frame (LOF), Loss Of Signal (LOS), APS failure. • Detects Line Alarm Indication(L-AIS), Line remote Defect Indication (L-RDI), Loss Of Pointer. • Detects Path Alarm Indication, Path remote Defect Indication, Path extended RDI. • Provides signal label monitor with PLM detection. • Supports path trace buffer with TIM-P and invalid message detection. • Computes and compares B3, REI-L and REI-P errors. • Computes and compares BIP-8 (B1, B2) and counts the errors.
3
XRT86SH221
PRELIMINARY
REV. P1.0.5
SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU
TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................ 1
FIGURE 1. SIMPLIFIED BLOCK DIAGRAM ............................................................................................................................................ 1 PACKAGE ORDERING INFORMATION ...................................................................................................... 1
FEATURES ........................................................................................................................ 2 TABLE OF CONTENTS...................................................................................................... I
1.0 PIN DESCRIPTIONS ................................................................................................................................ 4
1.1 MICROPROCESSOR INTERFACE PINS............................................................................................................ 4 1.2 BOUNDARY SCAN AND OTHER TEST PINS.................................................................................................... 6 1.3 GENERAL PURPOSE INPUT AND OUTPUT PINS............................................................................................ 7 1.4 TIMING AND CLOCK SIGNALS.......................................................................................................................... 7 1.5 LOW SPEED LINE INTERFACE SIGNALS ........................................................................................................ 9 1.6 HIGH SPEED SERIAL INTERFACE.................................................................................................................. 12 1.7 HIGH SPEED TELECOM BUS INTERFACE.................................................................................................... 13 1.8 HIGH SPEED SECTION AND PATH OVERHEAD BUS ................................................................................... 15 1.9 HIGH SPEED TU POH OVERHEAD BUS ......................................................................................................... 16 1.10 POWER AND GROUND PINS ......................................................................................................................... 18
2.0 APPLICATIONS AND PHYSICAL INTERFACE GENERAL OVERVIEW............................................. 20
FIGURE 2. APPLICATION DIAGRAM .................................................................................................................................................. 20
2.1 PHYSICAL INTERFACE .................................................................................................................................... 21
FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE PHYSICAL INTERFACE ............................................................................................. 21
2.2 TELECOM BUS INTERFACE ............................................................................................................................ 22
FIGURE 4. SIMPLIFIED BLOCK DIAGRAM OF THE TELECOM BUS INTERFACE ...................................................................................... 22
2.3 STM-0 SERIAL INTERFACE SDH FRAME SYNCHRONIZATION AND TIMING INTERFACE....................... 23
FIGURE 5. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL PORT INTERFACE ....................................................................................... 23
2.4 SDH FRAME SYNCHRONIZATION AND TIMING INTERFACE ...................................................................... 24
FIGURE 6. SIMP
