SINGLE T1/E1/J1 FRAMER/LIU COMBO

www.DataSheet4U.com PRELIMINARY PRELIMINARY MAY 2004 XRT86L30 REV. P1.0.1 SINGLE T1/E1/J1 FRAMER/LIU COMBO write the contents into the Receive HDLC buffers. The framer also contains a Transmit and Overhead Data Input port, which permits Data Link Terminal Equipment direct access to the outbound T1/E1/J1 frames. Likewise, a Receive Overhead output data port permits Data Link Terminal Equipment direct access to the Data Link bits of the inbound T1/E1/J1 frames. The XRT86L30 fully meets all of the latest T1/E1/J1 specifications: ANSI T1/E1.107-1988, ANSI T1/ E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/ E1.408-1990, AT&T TR 62411 (12-90) TR54016, and ITU G-703, G.704, G706 and G.733, AT&T Pub. 43801, and ETS 300 011, 300 233, JT G.703, JT G.704, JT G706, I.431. Extensive test and diagnostic functions include Loop-backs, Boundary scan, Pseudo Random bit sequence (PRBS) test pattern generation, Performance Monitor, Bit Error Rate (BER) meter, forced error insertion, and LAPD unchannelized data payload processing according to ITU-T standard Q.921. Applications and Features (next page) GENERAL DESCRIPTION The XRT86L30 is a single channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology (Relayless, Reconfigurable, Redundancy). The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86L30 provides protection from power failures and hot swapping. The XRT86L30 contains an integrated DS1/E1/J1 framer and LIU which provide DS1/E1/J1 framing and error accumulation in accordance with ANSI/ITU_T specifications. The framer has a framing synchronizer and transmit-receive slip buffers. The slip buffers can be independently enabled or disabled as required and can be configured to frame to the common DS1/ E1/J1 signal formats. The Framer block contains a Transmit and Receive T1/E1/J1 Framing function. There are 3 Transmit HDLC controllers which encapsulate contents of the Transmit HDLC buffers into LAPD Message frames. There are 3 Receive HDLC controllers which extract the payload content of Receive LAPD Message frames from the incoming T1/E1/J1 data stream and FIGURE 1. XRT86L30 1-CHANNEL DS1 (T1/E1/J1) FRAMER/LIU COMBO External Data Link Controller Local PCM Highway XRT86L30 Tx Overhead In Rx Overhead Out 1:2 Turns Ratio TTIP Tx Serial Data In Tx Serial Clock 2-Frame Slip Buffer Elastic Store Tx Framer Tx LIU Interface LLB LB TRING ST-BUS Rx Serial Data Out Rx Serial Clock 2-Frame Slip Buffer Elastic Store RTIP 1:1 Turns Ratio Rx Framer Rx LIU Interface RRING PRBS Generator & Analyser Performance Monitor HDLC/LAPD Controllers LIU & Loopback Control RxLOS 8kHz sync OSC Signaling & Alarms JTAG DMA Interface Line Side Microprocessor Interface Back Plane 1.544-16.384 Mbit/s 3 System (Terminal) Side TxON Memory INT D[7:0] µP A[11:0] Select 4 WR ALE_AS RD RDY_DTACK Intel/Motorola µP Configuration, Control & Status Monitor Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com XRT86L30 SINGLE T1/E1/J1 FRAMER/LIU COMBO REV. P1.0.1 PRELIMINARY • 3 Integrated HDLC controllers for transmit and receive, each controller having two 96-byte buffers (buffer 0 / buffer 1) • HDLC Controllers Support SS7 • Timeslot assignable HDLC • V5.1 or V5.2 Interface • Automatic Performance Report Generation (PMON Status) can be inserted into the transmit LAPD interface every 1 second or for a single transmission • Alarm Indication Signal with Customer Installation signature (AIS-CI) • Remote Alarm Indication with Customer Installation (RAI-CI) • Gapped Clock interface mode for Transmit and Receive. • Intel/Motorola and Power PC interfaces for configuration, control and status monitoring • Parallel search algorithm for fast frame synchronization • Wide choice of T1 framing structures: SF/D4, ESF, SLC®96, T1DM and N-Frame (non-signaling) • Direct access to D and E channels for fast transmission of data link information • PRBS, QRSS, and Network Loop Code generation and detection • Programmable Interrupt output pin • Supports programmed I/O and DMA modes of Read-Write access • Each framer block encodes and decodes the T1/ E1/J1 Frame serial data • Detects and forces Red (SAI), Yellow (RAI) and Blue (AIS) Alarms • Detects OOF, LOF, LOS errors and COFA conditions • Loopbacks: Local (LLB) and Line remote (LB) • Facilitates Inverse Multiplexing for ATM • Performance monitor with one second polling • Boundary scan (IEEE 1149.1) JTAG test port • Accepts external 8kHz Sync reference • 3.3V CMOS operation with 5V tolerant inputs • 128-pin TQFP package with -40°C to +85°C operation APPLICATIONS • High-Density T1/E1/J1 interfaces for Multiplexers, Switches, LAN Routers and Digital Modems • SONET/SDH terminal or Add/Drop multiplexers (ADMs) • T1/E1/J1 add/drop multiplexers (MUX) • Channel Service Units (CSUs): T1/E1/J1 and Fractional T1/E1/J1 • Digital Access Cross-connect System (DACs) • Digital Cross-connect Systems (DCS) • Frame Relay Switches and Access Devices (FRADS) • ISDN Primary Rate Interfaces (PRA) • PBXs and PCM channel bank • T3 channelized access concentrators and M13 MUX • Wireless base stations • ATM equipment with integrated DS1 interfaces • Multichannel DS1 Test Equipment • T1/E1/J1 Performance Monitoring • Voice over packet gateways • Routers FEATURES • Full duplex DS1 Tx and Rx Framer/LIU • Two 512-bit (two-frame) elastic store, PCM frame slip buffers (FIFO) on TX and Rx provide up to 8.192 MHz asynchronous back plane connections with jitter and wander attenuation • Supports input PCM and signaling data at 1.544, 2.048, 4.096 and 8.192 Mbits. Also supports 4channel multiplexed 12.352/16.384 (HMVIP/H.100) Mbit/s on the back plane bus (with stuffed don’t care bits for the other 3 channels) • Programmable output clocks for Fractional T1/E1/ J1 • Supports Channel Associated Signaling (CAS) • Supports Common Channel Signalling (CCS) • Supports ISDN Primary Rate Interface (ISDN PRI) signaling • Extracts and inserts robbed bit signaling (RBS) 2 XRT86L30 SINGLE T1/E1/J1 FRAMER/LIU COMBO PRELIMINARY ORDERING INFORMATION PART NUMBER XRT86L30IB PACKAGE 128 TQFP REV. P1.0.1 OPERATING TEMPERATURE RANGE -40°C to +85°C 3 XRT86L30 REV. P1.0.1 PRELIMINARY SINGLE T1/E1/J1 FRAMER/LIU COMBO LIST OF PARAGRAPHS 1.0 PIN LIST .................................................................................................................................................10 2.0 PIN DESCRIPTIONS ..............................................................................................................................11 3.0 MICROPROCESSOR INTERFACE BLOCK ..........................................................................................24 3.0.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ....................................................................................... 24 3.1 INTEL MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) .................................................................. 27 3.2 MOTOROLA MODE PROGRAMMED I/O ACCESS (SYNCHRONOUS) .......................................................... 29 3.2.1 DMA READ/WRITE OPERATIONS .............................................................................................................................. 31 3.3 MEMORY MAPPED I/O ADDRESSING ............................................................................................................ 33 3.4 DESCRIPTION OF THE CONTROL REGISTERS ............................................................................................ 34 3.4.1 REGISTER DESCRIPTIONS ......................................................................................................................................... 40 3.5 PROGRAMMING THE LINE INTERFACE UNIT (LIU SECTION) ................................................................... 124 3.6 THE INTERRUPT STRUCTURE WITHIN THE FRAMER ............................................................................... 143 3.6.1 CONFIGURING THE INTERRUPT SYSTEM, AT THE FRAMER LEVEL .................................................................. 146 4.0 GENERAL DESCRIPTION AND INTERFACE .....................................................................................149 4.1 PHYSICAL INTERFACE .................................................................................................................................. 149 4.2 R3 TECHNOLOGY (RELAYLESS / RECONFIGURABLE / REDUNDANCY) ................................................ 150 4.2.1 LINE CARD REDUNDANCY ....................................................................................................................................... 150 4.2.2 TYPICAL REDUNDANCY SCHEMES ........................................................................................................................ 150 4.2.3 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS .................................................................................................... 150 4.2.4 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY .................................................................................. 150 4.2.5 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY ..................................................................................... 151 4.3 POWER FAILURE PROTECTION ................................................................................................................... 152 4.4 OVERVOLTAGE AND OVERCURRENT PROTECTION ................................................................................ 152 4.5 NON-INTRUSIVE MONITORING ..................................................................................................................... 152 4.6 T1/E1 SERIAL PCM INTERFACE .............................................................................................