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XRT5794ES
Evaluation System
GENERAL DESCRIPTION The XR-T5794 demo board is a 4.75” x 9.75” double-sided circuit card that provides the support circuitry necessary for a comprhensive evaluation of the XR-T5794 CMOS Quad E1 Line Interface IC. three board-mounted DIP switches allow complete testing of all loop back, monitor, and transmitter power-down features. The demo board is normally supplied configured for 120W balanced E1 operation. However, the information contianed in this manual enables the user to modify the hardware for E1 unbalanced 75W cable service, or T1 balanced 100W use. BOARD OPERATION Figures 1, 2 and Table 2 are the board component layout, circuit diagram, and parts list respectively. The Demo Board uses the same pin function and signal names as the XR-T5794 data sheet. This user’s manual is designed to be used in conjuction with the XR-T5794 data sheet. The following description if for a demo board set up for balanced 120 W E1 use. It also applies to the other modes of operation if the appropriate impedence, cable type, and signal source changes are made. Power Requirements Power connections are made to banana jacks located in the upper left hand corner of the board. Power supply requirements are: VDD = +5.0 V ±5% at 850 mA maximum VSS = - 5.0 V ±5% at 850 mA minimum Line-Side Signals Receiver signal inputs are labeled RXIN1 through RXIN4 for the four channels. The connectors supplied for
balanced 120W operation are one quarter inch, 3-circuit audio type jacks. Equipment connections should be made with shielded twisted pair patch cords. The signal applied to any inputs must be a CCITT G.703 compliant pulse that may be attenuated by a twisted-pair cable. The XR-T5794 exceeds G.703 maximum cable loss of requirement of 6.0 dB at 1.024 MHz. Similarly, transmitter outputs are labeleds TXOUT1 through TXOUT4 for the four channels. The monitor channel output is labeled MONOUT. Connector types and connection methods are identical to those specified above for the recieve side. The transmitter output, when terminated by a 120W resistor, is a pulse meeting the G.703 template requirements. During demo board evaluation, all ransmitters, including the monitor channel, that are not powered down should be connected to either a properly terminated cable, a piece of test equipment contianing a termination, or a 120W load resistor. Equipment-Side Signal Connections For convenience, access to the logic-level equipment-side signals is provided by two groups of turret terminals and also by two ribbon cable connectors. The terminals are convient for simple tests while the ribbon cable connectors reduce the amount of wiring necessary to connect the entire equipment side of the demo board to customer equipment. Header P1 and a group of terminals that provide channel 1 and 2 I/O are located below the XR-T5794. For channels 3 and 4, P2 and a second group of pins are located above the XR-T5794. P1 and P2 are dual-row 26 pin headers with only the odd-nimbered pins used to carry signals. Even-numbered pins are grounded to minimize ribbon cable crosstalk. Pin 13 is also grounded to provide isolation between the transmit and receive directions.
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For P1 and P2 respectively, Table 1 and 2 presented below give the header pin, signal symbol, the corresponding XR-T5794 pin, and a brief description of the signal present.
P1 Pin 1 3 5 7 9 11 15 17 19 21 23 25 Symbol LOS1 LOS2 RXNEG1 RXPOS1 RXNEG2 RXPOS2 TXNEG1 TXPOS1 TXCLK1 TXNEG2 TXPOS2 TXCLK2 T5794 Pin 39 40 45 46 47 48 53 54 55 56 57 58 Signal Description Channel 1 - Receive Loss of Signal Output Channel 2 - Receive Loss of Signal Output Channel 1 - Receive Negative Rail Output Channel 1 - Receive Positive Rail Output Channel 2 - Receive Negative Rail Output Channel 2 - Receive Positive Rail Output Channel 1 - Transmit Negative Rail Input Channel 1 - Transmit Positive Rail Input Channel 1 - Transmit Clock Input Channel 2 - Transmit Negative Rail Input Channel 2 - Transmit Positive Rail Input Channel 2 - Trnasmit Clock Input
Table 1. Header P1 - Channel 1 and 2 Equipment Side I/O Connections
P2 Pin 1 3 5 7 9 11 15 17 19 21 23 25
Symbol TXCLK4 TXPOS4 TXNEG4 TXCLK3 TXPOS3 TXNEG3 RXPOS3 RXNEG3 RXPOS$ RXNEG4 LOS4 LOS3
T5794 Pin 12 13 14 15 16 17 22 23 24 25 30 31
Signal Description Channel 4 - Transmit Clock Input Channel 4 - Transmit Positive Rail Input Channel 4 - Transmit Negative Rail Input Channel 3 - Transmit Clock Input Channel 3 - Transmit Positive Rail Input Channel 3 - Transmit Negative Rail Input Channel 3 - Receive Positive rail Output Channel 3 - Recevie Negative Rail Output Channel 4 - Receive Positive Rail Output Channel 4 - Receive Negative Rail Output Channel 4 - Receive Loss of Signal Output Channel 3 - Receive Loss of Signal Outpu
Table 2. Header P2 - Channel 3 and 4 Equipment Side I/O Connections
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Equipment-Side Signal Characteristics All equipment-side connections at P1 and P2 are TTL logic-level compatible for the inputs and outputs. Specific signal types present at these pins are as follows. LOS1 Through LOS4 These pins are the loss signal outputs (LOS) for the for receive channels. A LOS output will go to a logic 1 state when the input applied to the corresponding receiver is less that the LOS threshold voltage. RXPOS1 Through RXPOS4 The signal present at these pins is the positive half of the dual-rail receive data. A positive bipolar input pulse at a receiver input will produce a positive-going pulse at the corresponding RXPOS output. Data pulse width at an RXPOS output is approximately equal to the width of the pulse applied to the reciever input at its 50% amplitude point. RXNEG1 Through RXNEG4 The signal present at these pins is the negative half of the dual-rail receive data. A negative bipolar input pulse at a receiver input will produce a positive-going pulse at the corresponding RXNEG output. Data pulse width is the same as described above for the RXPOS output. TXCLK1 Through TXCLK4 These pins are the transmit clock inputs of four transmit channels. For a specific channel, TXCLK is a 2.048 MHz 50% duty cycle square wave that is synchronized with the data to be transmitted over that channel. TXPOS1 Through TXPOS4 These pins are the positive rail inputs for the dual-rail transmit data for the four tranmit channels. A positive-going pulse at a TXPOS input will produce a positive bipolar outout pulse at the corresponding tranmitter output. The signal applied to a TXPOS input must be wider that the positive half cycle of the corresponding TXCLK, and must also meet the set-up and hold time specified in the XR-T5794 datasheet. When these conditions are met, the pulse width at the transmitter output TXOUT is determined by the positive going half-cycle of TXCLK . TXNEG1 Through TXNEG4 These pins are the negative rail input for the dual-rail transmit data for the four transmit channels. A positive-going pulse at a TXNEG input will produce a negative bipolar output pulse at the corresponding transmitter output. The pulse width conditions described above for the TXPOS input also apply to TXNEG. Operation Without TXCLK Operation without TXCLK is possible if this pin is connected to either DGND or DVDD. Transmit output pulse width in this mode of operation is determined by the widths of the pulsed applied to the TXPOS and TXNEG inputs. Therefore, the data applied to these inputs must be one-half width return-to-zero (RZ) pulses in order to produce a normal width bipolar transmit output pulse. DIP Switch Settings On the demo board, the logic levels presented at all control-type XR-T5794 input pins may be set with DIP switches. The following circuit is used to switch logic levels. Each IC input that is to be programmed has a 10 K W pull-up resistor connected to VDD. A SPAT DIP switch section is also connected between this input and ground. Therefore, when the switch lever is in the “ON” position as marked on the switch body, the IC input is at a “Logic 0” level. For convenience, a small “1” and “0” that indicate IC pin logic level to switch position correspondence is printed on the borad at the top end of each DIP switch.
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Tables 3, 4 and 5, which are given below, list the switch position, XR-T5794 pin controlled, signal symbol, and function of the three demo board DIP switches.
Switch Position 1 2 3 4 (Not Used) IC Pin 33 34 37 Symbol MSEL0 MSEL1 MSEL2 Switch Setting Off On Off On On Off Function MSEL0 = Logic 1 MSEL0 = Logic 0 MSEL1 = Logic 1 MSEL1 = Logic 0 MSEL2 = Logic 1 MSEL2 = Logic 0
Table 3. Dip Switch S1 Functions
Switch Position 1 2 3 4 5 6 7
IC Pin 61 62 60 52 51 50 42
Symbol TXEN2 TXEN1 ZSEL LPEN2 LPEN1 E1/T1B LPMOD2
Switch Setting Off On Off On Off On Off On Off On Off On Off On
Function Transmitter 2 Output Enabled Transmitter 2 Output High Impedence Transmitter 1 Output Enabled Transmitter 1 Output High Impedance 120 W Mode Selected 75 W Mode Selected Channel 2 Loop Mode Enabled Channel 2 Normal Operation Channel 1 Loop Mode Enabled Channel 1 Normal Operation E1 Mode Selected T1 Mode Selected Channel 2 Remote Loop Back Mode Selected Channel 2 Local Loop back Mode Selected Channel 1 remote Loopback Mode Selected Channel 1 Local Loop Back Mode Selected
8
41
LPMOD1
Off On
Table 4. Dip Switch S2 Functions
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Switch Position 1 IC Pin 28 Symbol LPMOD3 Switch Setting Off On 2 27 LPMOD4 Off On 3 (Not Used) 4 5 6 7 8 19 18 10 9 8 LPEN3 LPEN4 MONEN TXEN3 TXEN4 Off On Off On Off On Off On Off On Channel 3 Loop Mode Enabled Channel 3 Normal Operation Channel 4 Loop Made Enabled Channel 4 Normal Operation Monitor Output Enabled Monitor Output High Impedance Transmitter 3 Output Enabled Transmitter 3 Output High Impedance Transmitter 4 Output Enabled Transmitter 4 Output High Impedance Function Channel 3 Remote Loop Back Mode Selected Channel 3 Local Loop Back Mode Selected Channel 4 Remote Loop Back Mode Selecte
