INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER

www.DataSheet4U.com xr DECEMBER 2006 XRK799J93 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER REV. 1.0.1 GENERAL DESCRIPTION The XRK799J93 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other three pairs generate 2x, phase aligned clock outputs. External PLL feedback is used to also provide zero delay buffer performance. The XRK799J93 Intelligent Dynamic Clock Switch circuit continuously monitors both input CLK signals. Upon detection of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will FIGURE 1. BLOCK DIAGRAM OF THE XRK799J93 CLK _Selected INP1Bad INP0Bad Man_Override Alarm_Reset Sel_CLK be latched (H). If that CLK is the primary clock, the device will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance. The typical phase bump caused by a failed clock is eliminated. FEATURES • • • • • • Fully Integrated PLL Intelligent Dynamic Clock Switch LVPECL Clock Outputs LVCMOS Control I/O 3.3V Operation 32-Lead TQFP Packaging Dynamic Switch Logic Qb0 Qb0 Qb1 Qb1 ÷2 Qb2 Qb2 Qa0 Qa0 Qa1 Qa1 CLK0 CLK0 CLK1 CLK1 Ext_FB Ext_FB PLL_En MR PLL 160-380MHz ÷4 Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com XRK799J93 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER PRODUCT ORDERING INFORMATION PRODUCT NUMBER XRK799J93IQ PACKAGE TYPE 32-Lead TQFP OPERATING TEMPERATURE RANGE -40°C to +85°C FIGURE 2. PIN OUT OF THE XRK799J93 VCC 24 23 22 21 20 19 18 Qa1 Qa1 Qa0 Qa0 VCC VCCA Man_Override PLL_En 17 VCC Qb0 Qb0 Qb1 Qb1 Qb2 Qb2 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 16 15 14 VCC Inp0bad Inp1bad CLK_Selected GND Ext_FB Ext_FB GND XRK799J93 13 12 11 10 9 Alarm_Reset CLK0 CLK0 CLK1 CLK1 2 Sel_CLK GND MR rx REV. 1.0.1 rx REV. 1.0.1 XRK799J93 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER PIN DESCRIPTIONS PIN NAME TYPE DESCRIPTION CLK0, CLK0 CLK1, CLK1 LVPECL Input LVPECL Input LVPECL Input LVPECL Output LVPECL Output Clock 0 - Differential PLL clock reference (CLK0 pulldown, CLK0 pulldown) Clock 1 - Differential PLL clock reference (CLK1 pulldown, CLK1 pulldown) Differential PLL feedback clock (Ext_FB pulldown, Ext_FB pulldown) Differential 1x output pairs, connect one QaX pair to Ext_FB Differential 2x output pairs Indicates detection of a bad input reference Clock 0 with respect to the feedback signal. The output is active HIGH and will remain HIGH until the alarm reset is asserted. Indicates detection of a bad input reference Clock 1 with respect to the feedback signal. The output is active HIGH and will remain HIGH until the alarm reset is asserted. 0 - if CLK0 is selected 1 - if CLK1 is selected 0 - will reset the input bad flags and align CLK_Selected with Sel_CLK. The input is one-shotted 1 - normal operation (50KΩ pullup). 0 - selects CLK0 1 - selects CLK1 (50kΩ pulldown) 0 - normal operation 1 - disables internal clock switch circuitry (50KΩ pulldown). 0 - bypasses the phase-locked loop, input CLKx directly drives divider block 1 - selected input reference applied to PLL (50KΩ pullup). 0 - resets the internal dividers forcing outputs LOW. Asynchronous to the clock 1 - normal operation (50KΩ pullup). PLL power supply Digital power supply PLL Ground Digital Ground Ext_FB, Ext_FB Qa[1:0], Qa[1:0] Qb[2:0], Qb[2:0] Inp0bad LVCMOS Output Inp1bad CLK_Selected LVCMOS Output LVCMOS Output Alarm_Reset Sel_CLK LVCMOS Input LVCMOS Input Man_Override LVCMOS Input PLL_En LVCMOS Input MR LVCMOS Input VCCA VCC GNDA GND Power Supply Power Supply Power Supply Power Supply 3 XRK799J93 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER ABSOLUTE MAXIMUM RATINGSa SYMBOL CHARACTERISTICS MIN MAX U NIT VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -0.3 -0.3 -0.3 3.9 VCC+0.3 V V V +20 +50 -65 125 mA mA °C a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. GENERAL SPECIFICATIONS SYMBOL CHARACTERISTICS MIN TYP MAX UNIT CONDITION VTT MM HBM LU CIN θJA Output termination voltage ESD Protection (Machine model) ESD Protection (Human body model) Latch-up immunity Input Capacitance Thermal resistance junction to ambient JESD 51-3, single layer test board JESD 51-6, multilayer test board 200 2000 200 VCC-2 V V V mA 4.0 pF Natural convection 62.0 47 14 115 °C/W °C/W °C/W °C θJC Thermal resistance junction to case Operating junction temperature 4 rx REV. 1.0.1 CONDITION Inputs rx REV. 1.0.1 XRK799J93 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER DC C HARACTERISTICS (VCC= 3.3 + 5%, TA= -40°C TO +85°C) SYMBOL CHARACTERISTICS MIN TYP MAX UNIT CONDITION LVCMOS control inputs (MR, PLL_En, Sel_CLK, Man_Override, Alarm_Reset) VIH VIL Input voltage high Input voltage low Man_Override, Sel_CLK (pull down) IIN Input Current PLL_En, MR, Alarm_Reset (pull up) -100 2.0 VCC+0.3 0.8 100 V V μA μA VIN=VCC VIN=GND LVCMOS Control Outputs VOH VOL Output High Voltage Output Low Voltage 2.0 0.55 V V IOH=-10mA IOL=10mA LVPECL clock inputs (CLK, CLK)b IIN Input current +100 μΑ VIN =VCC or VIN =GND LVPECL clock outputs (Qa[1:0], Qa[1:0], Qb[2:0], Qb[2:0]) VOH VOL Output high voltage Output low voltage VCC-1.2 VCC-1.9 VCC-0.7 VCC-1.45 V V Termination 50Ω to VTT Termination 50Ω to VTT Supply Current IGND ICCPLL Maximum ground supply current - gnd pins Maximum PLL power supply - VCC_PLL pin 180 15 mA mA GND pins V CCPLL pin a. Inputs have internal pullup/pulldown resistors which affect the input current. b. Clock inputs driven by LVPECL compatible signals. 5 XRK799J93 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER AC C HARACTERISTICS (VCC= 3.3 + 5%, TA= -40°C TO +85°C) f SYMBOL PARAMETER MIN ÷4 feedback TYP MAX UNIT fref fVCO fMAX frefDC tpd Input Reference Frequency PLL VCO Lock Range Output Frequency 40 160 95 380 95 190 75 MHz MHz MHz Qa[1:0] Qb[2:0] 40 80 25 Reference Input Duty Cycle Propagation Delay CLKn to Ext_FB (SPO) c CLKn to Q (Bypass) % -150 150 5 1.3 VCC-0.3 ps ns V V VPP VCMR tskew Differential peak-to-peak input voltage g Differential input crosspoint voltage h Output-to-Output Skew Within Qa[1:0] or Qb[2:0] All outputs 0.25 VCC-1.7 50 80 ps Δper/cycle Rate of change of periods Qa[1:0] d Qb[2:0] d Qa[1:0] Qb[2:0] e e 50 25 400 200 45 55 40 10 50 700 ps/ cycle DC tjitter tlock tr/tf Output duty cycle Cycle-to-cyle jitter, Standard deviation (RMS) Maximum PLL lock time Output Rise/Fall time % ps ms ps @ fref =75MHZ c. Static phase offset between the selected reference clock and the feedback signal. d. Specification holds for a clock switch between two signals no greater than 400ps out of phase. Delta period change per cycle is averaged over the clock switch excursion. (See Applications Information section for more detail) e. Specification holds for a clock switch between two signals no greater than ±π out of phase. Delta period change per cycle is averaged over the clock switch excursion. f. PECL output termination is 50 ohms to VCC – 2.0V. g. VPP is the minimum differential input voltage swing required to maintain AC characteristic including SPO, device and part-to-part skew. Applicable to CLK0, CLK1 and Ext_FB. h. VCMR is the crosspoint of the differential input signal. Normal operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP specification. Violation of VCMR or VPP impacts the SPO, device and part-to-part skew. Applicable to CLK0, CLK1 and Ext_FB. 6 rx REV. 1.0.1 CONDITION Locked Qa output used for feedback PLL_En=1 PLL_En=0 Inp0bad, Inp1bad: Inp0bad is latched (H) when CLK0 is stuck (H) or (L) for at least one Ext_FB period, or if one of the inputs CLK0 or CLK0 is floating. Inp1bad is latched (H) when CLK1 is stuck (H) or (L) for at least one Ext_FB period, or if one of the inputs CLK1 or CLK1 is floating. Both Inp0bad and Inp1bad are latched (H) when Ext_FB is stuck (H) or (L) for at least one Qa period, or if one of the inputs Ext_FB or Ext _FB is floating. Both Inp0bad and Inp1bad are cleared (L) on assertion of Alarm_Reset. The status functions Inp0bad and Inp1bad are active for Man_Override (H) or (L). CONTROL FUNCTIONS Sel_Clk: Sel_Clk (L) selects CLK0 as the primary clock. Sel_Clk (H) selects CLK1 as the primary clock. Alarm_Reset: Asserted by a negative edge. Generates a one–shot reset pulse that clears INPUT_BAD latches and Clk_Selected latch. PLL_En: While (L), the PLL reference signal is substituted for the VCO output. MR: While (L), internal dividers are held in reset which holds all Q outputs LOW. MAN OVERRIDE (H) (IDCS is disabled, PLL functions normally). PLL reference signal (as indicated by Clk_Selected) will always be the CLK selected by Sel_Clk. If Ext_FB misses at least one pulse, Qa and Qb outputs will drop to a minimum frequency (~20MHz) for 1-uS, or until Ext_FB shows any activity, whichever is longer. This prevents the Qa and Qb frequencies from rising due the PLL incorrectly interpreting an intermittent Ext_FB as a VCO running too slow. MAN OVERRIDE (L) Intelligent Dynamic Clock Switch is enabled. The first CLK to fail will latch it’s INP_BAD (H) status flag and select the other input as the Clk_Selected for the PLL reference clock. Once latched, the Clk_Selected and INP_BAD remain latched until assertion of Alarm_Reset which clears all latches (INP_BADs are cleared and Clk_Selected = Sel_Clk)