INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER

www.DataSheet4U.com xr MARCH 2005 PRELIMINARY XRK7955 REV. P1.0.1 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER be latched (H). If that CLK is the primary clock, the device will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance. The typical phase bump caused by a failed clock is eliminated. FEATURES GENERAL DESCRIPTION The XRK7955 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other three pairs generate 5x, phase aligned clock outputs. External PLL feedback is used to also provide zero delay buffer performance. The XRK7955 Intelligent Dynamic Clock Switch circuit continuously monitors both input CLK signals. Upon detection of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will FIGURE 1. BLOCK DIAGRAM OF THE XRK7955 • Fully Integrated PLL • Intelligent Dynamic Clock Switch • LVPECL Clock Outputs • LVCMOS Control I/O • 3.3V Operation • 32-Lead LQFP Packaging CLK_Selected INP1Bad INP0Bad Man_Override Alarm_Reset Sel_CLK Dynamic Switch Logic PLL_En Qb0 Qb0 Qb1 Qb1 ÷2 Qb2 Qb2 Qa0 Qa0 Qa1 Qa1 OR CLK0 CLK0 CLK1 CLK1 Ext_FB Ext_FB MR PLL 200-400MHz ÷10 Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com xr REV. P1.0.1 PRELIMINARY XRK7955 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER PRODUCT ORDERING INFORMATION PRODUCT NUMBER XRK7955 PACKAGE TYPE 32-Lead LQFP OPERATING TEMPERATURE RANGE -40°C to +85°C FIGURE 2. PIN OUT OF THE XRK7955 VCC 24 23 22 21 20 19 18 Qa1 Qa1 Qa0 Qa0 VCC VCC_PLL Man_Override PLL_En 17 VCC Qb0 Qb0 Qb1 Qb1 Qb2 Qb2 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 16 15 14 VCC Inp0bad Inp1bad CK_Selected GND Ext_FB Ext_FB GND XRK7955 13 12 11 10 9 Alarm_Reset Sel_CLK CLK0 CLK0 CLK1 2 CLK1 GND MR XRK7955 PRELIMINARY INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER xr REV. P1.0.1 PIN DESCRIPTIONS PIN NAME CLK0, CLK0 CLK1, CLK1 Ext_FB, Ext_FB Qa[1:0], Qa[1:0] Qb[2:0], Qb[2:0] Inp0bad TYPE LVPECL Input LVPECL Input LVPECL Input LVPECL Output LVPECL Output LVCMOS Output DESCRIPTION Differential PLL clock reference (CLK0 pulldown, CLK0 pullup) Differential PLL clock reference (CLK1 pulldown, CLK1 pullup) Differential PLL feedback clock (Ext_FB pulldown, Ext_FB pullup) Differential 1x output pairs Differential 5x output pairs Indicates detection of a bad input reference clock 0 with respect to the feedback signal. The output is active HIGH and will remain HIGH until the alarm reset is asserted. Indicates detection of a bad input reference clock 1 with respect to the feedback signal. The output is active HIGH and will remain HIGH until the alarm reset is asserted. 0 - if clock 0 is selected 1 - if clock 1 is selected 0 - will reset the input bad flags and align Clk_Selected with Sel_Clk. The input is one-shotted (50KΩ pullup). 0 - selects CLK0 1 - selects CLK1 (40kΩ pulldown) 1 - disables internal clock switch circuitry (40KΩ pulldown). 0 - bypasses selected input reference around the phase-locked loop (50KΩ pullup). 0 - resets the internal dividers forcing Q outputs LOW. Asynchronous to the clock (50KΩ pullup). PLL power supply Digital power supply PLL Ground Digital Ground Inp1bad LVCMOS Output Clk_Selected Alarm_Reset Sel_Clk Manual_Override PLL_En MR VCCA VCC GNDA GND LVCMOS Output LVCMOS Input LVCMOS Input LVCMOS Input LVCMOS Input LVCMOS Input Power Supply Power Supply Power Supply Power Supply 3 xr REV. P1.0.1 PRELIMINARY XRK7955 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER ABSOLUTE MAXIMUM RATINGSa SYMBOL VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 CHARACTERISTICS MIN -0.3 -0.3 -0.3 MAX 3.6 VCC+0.3 VCC+0.3 +20 +50 125 UNIT V V V mA mA °C CONDITION a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. GENERAL SPECIFICATIONS SYMBOL VTT MM HBM LU CIN θJA CHARACTERISTICS Output termination voltage ESD Protection (Machine model) ESD Protection (Human body model) Latch-up immunity Input Capacitance Thermal resistance junction to ambient JESD 51-3, single layer test board JESD 51-6, 2S2P multilayer test board θJC Thermal resistance junction to case Operating junction temperature 200 2000 200 4.0 MIN TYP VCC-2 MAX UNIT V V V mA pF Inputs CONDITION 62.0 47.0 14 115 °C/W °C/W °C/W °C Natural convection Natural convection 4 XRK7955 PRELIMINARY INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER DC CHARACTERISTICS (VCC= 3.3 + 5%, TA= -40°C TO +85°C) SYMBOL CHARACTERISTICS MIN TYP MAX UNIT xr REV. P1.0.1 CONDITION LVCMOS control inputs (MR, PLL_En, Sel_CLK, Man_Override, Alarm_Reset) VIH VIL IIN Input voltage high Input voltage low Input currenta 100 2.0 VCC+0.3 0.8 -150 V V µΑ VIN =VCC or VIN =GND LVCMOS Control Outputs VOH VOL Output High Voltage Output Low Voltage 2.0 0.55 V V IOH=-10mA IOL=10mA LVPECL clock inputs (CLK, CLK)b IIN Input current +100 µΑ VIN =VCC or VIN =GND LVPECL clock outputs (Qa[1:0], Qa[1:0], Qb[2:0], Qb[2:0]) VOH VOL Output high voltage Output low voltage VCC-1.2 VCC-1.9 VCC-0.7 VCC-1.45 V V Termination 50Ω to VTT Termination 50Ω to VTT Supply Current IGND ICCPLL Maximum ground supply current - gnd pins Maximum PLL power supply - VCC_PLL pin 180 15 mA mA GND pins VCCPLL pin a. Inputs have internal pullup/pulldown resistors which affect the input current. b. Clock inputs driven by LVPECL compatible signals. 5 xr REV. P1.0.1 PRELIMINARY XRK7955 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER AC CHARACTERISTICS (VCC= 3.3 + 5%, TA= -40°C TO +85°C) (NOTE 5) f SYMBOL fref fVCO fMAX PARAMETER Input Reference Frequency PLL VCO Lock Range Output Frequency Qa[1:0] Qa[1:0] frefDC tpd Reference Input Duty Cycle Propagation Delay CLKn to Ext_FB (SPO) c CLKn to Q (Bypass) VPP VCMR tskew Differential input voltage (peak-to-peak) Differential input crosspoint voltage Output Skew Within Qa[1:0] or Qb[2:0] All outputs Rate of change of periods Qa[1:0]d Qb[2:0]d Qa[1:0]e Qb[2:0] tpw tjitter tlock tr/tf Output duty cycle Cycle-to-cyle jitter, Standard deviation (RMS) Maximum PLL lock time Output Rise/Fall time 50 e MIN ÷10 feedback 20 200 TYP MAX 40 400 UNIT MHz MHz MHz CONDITION Locked Qa Output used for feedback 20 100 25 40 200 75 % -150 150 5 1.3 VCC-0.3 50 80 ps ns V V PLL_EN = 1 PLL_EN = 0 0.25 VCC-1.7 ps ps ps/cycle ∆per/cycle 50 25 400 200 45 55 40 10 700 % ps ms ps @fref = 30MHz c. Static phase offset between the selected reference clock and the feedback signal. d. Specification holds for a clock switch between two signals no greater than 400ps out of phase. Delta period change per cycle is averaged over the clock switch excursion. (See Applications Information section for more detail) e. Specification holds for a clock switch between two signals no greater than ±π out of phase. Delta period change per cycle is averaged over the clock switch excursion. f. PECL output termination is 50 ohms to VCC – 2.0V. g. VPP is the minimum differential input voltage swing required to maintain AC characteristic including SPO, device and part-to-part skew. Applicable to CLK0, CLK1 and Ext_FB. h. VCMR is the crosspoint of the differential input signal. Normal operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP specification. Violation of VCMR or VPP impacts the SPO, device and part-to-part skew. Applicable to CLK0, CLK1 and Ext_FB. 6 XRK7955 PRELIMINARY INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER APPLICATIONS INFORMATION The XRK7955 is a dual clock PLL with on–chip Intelligent Dynamic Clock Switch circuitry. DEFINITIONS primary clock: The input CLK selected by Sel_Clk. secondary clock: The input CLK NOT selected by Sel_Clk. xr REV. P1.0.1 PLL reference signal: The CLK selected as the PLL reference signal by Sel_Clk or the Intelligent Dynamic Clock Switch. The Intelligent Dynamic Clock Switch can override Sel_Clk. STATUS FUNCTIONS Clk_Selected: Clk_Selected (L) indicates CLK0 is selected as the PLL reference signal. Clk_Selected (H) indicates CLK1 is selected as the PLL reference signal. Inp0bad, Inp1bad: Inp0bad is latched (H) when CLK0 is stuck (H) or (L) for at least one Ext_FB period, or if one of the inputs CLK0 or CLK0 is floating. Inp1bad is latched (H) when CLK1 is stuck (H) or (L) for at least one Ext_FB period, or if one of the inputs CLK1 or CLK1 is floating. Both Inp0bad and Inp1bad are latched (H) when Ext_FB is stuck (H) or (L) for at least one Qa period, or if one of the inputs Ext_FB or Ext _FB is floating. Both Inp0bad and Inp1bad are cleared (L) on assertion of Alarm_Reset. The status functions Inp0bad and Inp1bad are active for Man_Override (H) or (L). CONTROL FUNCTIONS Sel_Clk: Sel_Clk (L) selects CLK0 as the primary clock. Sel_Clk (H) selects CLK1 as the primary clock. Alarm_Reset: Asserted by a negative edge. Generates a one–shot reset pulse that clears INPUT_BAD latches and Clk_Selected latch. PLL_En: While (L), the PLL reference signal is substituted for the VCO output. MR: While (L), internal dividers are held in reset which holds all Q outputs LOW. MAN OVERRIDE (H) (IDCS is disabled, PLL functions normally). PLL reference signal (as indicated by Clk_Selected) will always be the CLK selected by Sel_Clk. If Ext_FB misses at least one pulse, Qa and Qb outputs will drop to a minimum frequency (~20MHz) for 1-uS, or until Ext_FB shows any activity, whichever is longe