1:12 LVCMOS PLL CLOCK GENERATOR

www.DataSheet4U.com APRIL 2006 PRELIMINARY XRK69772 REV. P1.0.0 1:12 LVCMOS PLL CLOCK GENERATOR GENERAL DESCRIPTION The XRK69772 is a PLL based LVCMOS Clock Generator targeted for high performance and low skew clock distribution applications. The XRK69772 can select between one of three reference inputs and provides 14 LVCMOS outputs -12 outputs (3 banks of 4) for clock distribution, 1 for feedback and 1 for synchronization. The XRK69772 is a highly flexible device. It can be configured to accept either a crystal oscillator input or one of two LVCMOS compatible inputs for use as the input reference clock source. To support clock redundancy, two LVCMOS inputs are provided. Switching the internal reference clock is controlled by the control input, CLK_SEL. The XRK69772 uses PLL technology to frequency lock its outputs to the input reference clock. The divider in the feedback path will determine the frequency of the VCO. Each of the separate output banks can individually divide down the VCO output frequency. This allows the XRK69772 to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. The outputs of the XRK69772 can individually be immobilized, in the low state, by use of the stop clock feature. All outputs except QC0 and QFB can be immobilized through a 2 pin serial interface. Global output disabling and reset can be achieved the control input MR/OE. The XRK69772 also has a QSYNC output which can be used for system synchronization purposes. It monitors Bank A and Bank C outputs and goes low one period of the faster clock prior to coincident rising edges of Bank A and Bank C clocks. QSYNC then goes high again when the coincident rising edges of Bank A and Bank C occur. This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer multiples of one another. The XRK69772 has an output frequency range of 8.33MHz to125MHz and an input frequency range of 5MHz to 120MHz. FEATURES • Fully Integrated PLL • Selectable crystal oscillator or LVCMOS inputs for reference clock source • 14 LVCMOS outputs ■ 3 banks with 4 outputs each. Frequencies can be individually controlled by bank 1 dedicated feedback with frequency control 1 Sync ■ ■ • • • • VCO Range 200MHz to 480MHz Output freq. range: 5MHz to 240MHz Max Output Skew of 250ps Cycle-to-cycle jitter: 150ps (typ) APPLICATIONS • System Clock generator • Zero Delay Buffer PRODUCT ORDERING INFORMATION PRODUCT NUMBER XRK69772CR XRK69772IR PACKAGE TYPE 52-LEAD LQFP 52-LEAD LQFP OPERATING TEMPERATURE RANGE 0°C to +70°C -40°C to +85°C Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com XRK69772 1:12 LVCMOS PLL CLOCK GENERATOR PRELIMINARY REV. P1.0.0 FIGURE 1. B LOCK D IAGRAM OF THE XRK69772 STOP XTAL1 XTAL2 XTAL QA0 0 VDD 1 0 Ref VCO ÷2 DIVIDER SELECT 0 0 1 BANK A BANK B BANK C ÷4, ÷6, ÷8, ÷12 ÷4, ÷6, ÷8, ÷10 STOP QA1 CLK0 STOP QA2 CLK1 CLK_SEL 1 PLL 200-480MHz VDD 1 ÷2, ÷4, ÷6, ÷8 ÷4, ÷6, ÷8, ÷10, ÷12, ÷16, ÷20 STOP QA3 FB STOP QB0 Sync Pulse REF_SEL FB_IN VCO_SEL PLL_EN STOP QB1 FB STOP QB2 STOP QB3 VDD QC0 FSEL_A[0:1] FSEL_B[0:1] FSEL_C[0:1] FSEL_FB[0:2] 2 2 2 3 STOP QC1 0 STOP QC2 1 VDD INV_CLK STOP QC3 POWER-ON RESET QFB STOP STOP_DATA STOP_CLK MR/OE QSYNC SERIAL INTERFACE 12 FIGURE 2. PIN OUT OF THE XRK69772 VCO_SEL FSEL_A0 FSEL_A1 FSEL_B0 41 FSEL_B1 40 39 38 37 36 35 34 GND GND VDD VDD 45 QA0 QA1 QA2 GND ___ MR/OE STOP_CLK STOP_DATA FSEL_FB2 PLL_EN REF_SEL CLK_SEL CLK0 CLK1 XTAL1 XTAL2 VDD_PLL 52 1 2 3 4 5 6 7 8 9 10 11 12 13 14 51 50 49 48 47 46 44 QA3 43 42 GND QB0 VDD QB1 GND QB2 VDD QB3 FB_IN GND QFB VDD FSEL_FB0 XRK69772 33 32 31 30 29 28 15 16 17 18 19 20 21 22 23 24 25 27 26 GND GND QC3 QC2 QC1 QC0 INV_CLK FSEL_C1 FSEL_C0 QSYNC VDD VDD 2 FSEL_FB1 PRELIMINARY REV. P1.0.0 XRK69772 1:12 LVCMOS PLL CLOCK GENERATOR PIN DESCRIPTIONS PIN # 1, 15, 24, 30, 35, 39, 47, 51 2 3 4 5, 26, 27 6 7 8 9,10 11 12 13 14 16, 18, 21, 23 17, 22, 33, 37, 45, 49 19, 20 25 28 29 31 32, 34, 36, 38 40, 41 42, 43 44, 46, 48, 50 52 NAME GND MR/OE STOP_CLK STOP_DATA FSEL_FB[2:0] PLL_EN REF_SEL CLK_SEL CLK0, CLK1 XTAL1 XTAL2 VDD_PLL INV_CLK QC[3:0] VDD FSEL_C[1:0] QSYNC VDD QFB FB_IN QB[3:0] FSEL_B[1:0] FSEL_A[1:0] QA[3:0] VCO_SEL TYPE POWER INPUT* INPUT* INPUT* INPUT* INPUT* INPUT* INPUT* INPUT* INPUT OUTPUT POWER INPUT* OUTPUT POWER INPUT* OUTPUT POWER OUTPUT INPUT* OUTPUT INPUT* INPUT* OUTPUT INPUT* Power supply ground Master reset and output enable. High = output enabled, Low = device reset & outputs tri-stated Clock input for serial control. Data input for serial control Select inputs for control of feedback divide value. PLL bypass. High = PLL, Low = PLL bypass Xtal or CLKx select. High = Xtal input selected, Low = CLK0 or CLK1 selected CLK0 or CLK1 Select. High = CLK1selected, Low = CLK0 selected Reference clock inputs. Crystal oscillator input Crystal oscillator output Analog supply for PLL Invert clock select for QC3 & QC2. High = invert, Low = normal operation Clock outputs (Bank C) Power supply for outputs. Bank C divide select pins. Synchronization output for Bank A and Bank C. Power supply for core. Feedback clock output Feedback input Clock outputs (Bank B) Bank B divide select pins. Bank A divide select pins. Clock outputs (Bank A) VCO select. High = VCO/1, Low = VCO/2. DESCRIPTION * 25KΩ pull-up resistor 3 XRK69772 1:12 LVCMOS PLL CLOCK GENERATOR 1.0 DEVICE SPECIFICATIONS TABLE 1: GENERAL SPECIFICATIONS SYMBOL VTT ESDMM ESDHBM LU CIN CHARACTERISTICS Output Termination Voltage ESD Protection (Machine model) ESD Protection (Human body model) Latch-up Immunity Input capacitance PRELIMINARY REV. P1.0.0 CONDITION MIN TYP MAX UNIT VDD÷2 200 2000 200 per input 4 V V V mA pf TABLE 2: ABSOLUTE MAXIMUM RATINGS SYMBOL VDD VIN VOUT IIN IOUT TS CHARACTERISTICS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature -65 CONDITION MIN TYP MAX UNIT -0.3 -0.3 -0.3 3.9 VDD + 0.3 VDD + 0.3 +/-20 +/-50 125 V V V mA mA C TABLE 3: DC CHARACTERISTICS (VDD = 3.3V +/- 5%) SYMBOL VDD_PLL VIH VIL VOH VOL ZOUT IPU IDD_PLL IDDQ CHARACTERISTICS PLL Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage IOH = -24mA IOL = 24mA IOL = 12mA 14 -17 VIN = GND or VDD @ VDD_PLL Pin All VDD pins -100 8 200 13.5 35 2.4 0.55 0.30 CONDITION MIN TYP MAX UNIT 3.0 2.0 VDD VDD + 0.3 0.8 V V V V V Ω μA mA mA Output Impedance Input Current PLL Supply Current Quiescent Supply Current 4 PRELIMINARY REV. P1.0.0 XRK69772 1:12 LVCMOS PLL CLOCK GENERATOR TABLE 4: AC CHARACTERISTICS (VDD = 3.3V +/- 5%) SYMBOL fREF CHARACTERISTICS Input reference frequencya CONDITION MIN TYP MAX UNIT ÷4 feedback ÷6 feedback ÷8 feedback ÷10 feedback ÷12 feedback ÷16 feedback ÷20 feedback ÷24 feedback ÷32 feedback ÷40 feedback PLL bypass mode 50.0 33.3 25.0 20.0 16.6 12.5 10.0 8.33 6.25 5.00 120 80.0 60.0 48.0 40.0 30.0 24.0 20.0 15.0 12.0 250 480 25 240.0 120.0 80.0 60.0 48.0 40.0 30.0 24.0 20.0 20.0 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ns fVCO fXTAL fMAX VCO frequency range Crystal input frequency range Output frequencya ÷2 output ÷4 output ÷6 output ÷8 output ÷10 output ÷12 output ÷16 output ÷20 output ÷24 output 200 10 100.0 50.0 33.3 25.0 20.0 16.6 12.5 10.0 8.33 fSTOP_CLK tPW ItR, ItF t(∅) Serial interface max. frequency CLKx pulse min. width Input CLKx Rise/Fall time Propagation Delay (static 0.8V to 2.0V 6.25MHz < fREF < 65.0MHz fREF = 50MHz & FB = ÷8 -3 -4 -166 2.0 1.0 +3 +4 +166 100 100 100 250 (T÷2)-200 T÷2 (T÷2)+200 1.0 ns ° ° ps ps ps ps ps ps ns phase offset) CLKx to FB_INb 65.0MHz < fREF < 125MHz tSK(O) Output to output skewc Bank A (QAx to QAy) Bank B (QBx to QBy) Bank C (QCx to QCy) all outputs (QXy to QWz) DC OtR, OtF Output duty cycled Output Rise/Fall time 0.55V to 2.4V 0.1 5 XRK69772 1:12 LVCMOS PLL CLOCK GENERATOR PRELIMINARY REV. P1.0.0 TABLE 5: AC CHARACTERISTICS (CON’T) (VDD = 3.3V +/- 5%) SYMBOL tPLZ, tPHZ tPZL, tPZH tJIT(CC) tJIT(PER) tJIT(I/O)RMS CHARACTERISTICS Output Disable Time Output Enable Time Cycle-to-Cycle Jitter Period Jitter I/O Jitter (RMS) VCO @ 400MHz All outputs in same divider configuration All outputs in same divider configuration ÷4 feedback ÷6 feedback ÷8 feedback ÷10 feedback ÷12 feedback ÷16 feedback ÷20 feedback ÷24 feedback ÷32 feedback ÷40 feedback ÷4 feedback ÷6 feedback ÷8 feedback ÷10 feedback ÷12 feedback ÷16 feedback ÷20 feedback ÷24 feedback ÷32 feedback ÷40 feedback 1.20-3.5 0.70-2.50 0.50-1.80 0.45-1.20 0.30-1.00 0.25-0.70 0.20-0.55 0.17-0.40 0.12-0.30 0.11-0.28 10 150 CONDITION MIN TYP MAX UNIT 8 8 200 150 11 86 13 88 16 19 21 22 27 30 ns ns ps ps ps ps ps ps ps ps ps ps ps ps MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ns BW PLL closed loop bandwidth tLOCK NOTES: Max PLL Lock Time a. PLL locked, except when configured in bypass mode. b. t(Ø)[s] = t(Ø)[°] ÷ (fref x 360°) c. Not including Qsync output d. T is the output period. FIGURE 3. TEST LOAD Transmission Line Z = 50Ω 50Ω VTT 6 PRELIMINARY REV. P1.0.0 XRK69772 1:12 LVCMOS PLL CLOCK GENERATOR 2.0 CONFIGURATION TABLES TABLE 6: FUNCTION CONTROLS CONTROL PIN MR/OE PLL_SEL LOGIC 0 Resets the output divide circuitry and serial interface, tri-states all outputs PLL bypass mode enabled. This is a test mode in which the reference clock is provided to the output dividers in place of the VCO. CLKx selected as ref source to PLL CLK0 selected QC2 & QC3 are in phase with QC1 & QC4 VCO ÷ 2 LOGIC 1 Enables all outputs - normal operation PLL enabled - normal operation REF_SEL CLK_SEL INV_CLK VCO_SEL Crystal Oscillator selected as ref source