3.3V PROGRAMMABLE SKEW CLOCK BUFFER

www.DataSheet4U.com FEBRUARY 2007 XRK4993 3.3V PROGRAMMABLE SKEW CLOCK BUFFER REV. 1.0.0 FUNCTIONAL DESCRIPTION The XRK4993 is a 3.3V High-Speed Low-Voltage Programmable Skew Clock Buffer. It is intended for high-performance computer systems and offers user selectable control over system clock functions to optimize timing. Eight ouputs, arranged in four banks, can each drive 75Ω terminated transmission lines while delivering minimal and specified output skews and full-swing Low Voltage TTL logic levels. Banks A, B, C (two outputs per bank) can be individually selected for one of nine delay or function configurations through two dedicated three-level inputs. These outputs are able to lead or lag the CLKIN input reference clock by up to 6 time units from their nominal "zero" skew position. The integrated PLL allows external load and transmission line delay effects to be canceled achieving zero delay capability. Combining the zero delay capability with the selectable output skew functions, output-to-output delays of up to +12 time units can be created. The XRK4993’s divide functions (divide-by-two and divide-by-four) allow distribution of a low-frequency clock that can be multiplied by two or four at the clock destination. This feature facilitates clock distribution while allowing maximum system clock flexibility. When the OE pin is held low, all the outputs are synchronously enabled. However, if OE is held high, FIGURE 1. BLOCK DIAGRAM OF THE XRK4993 all the outputs except synchronously disabled. QC0 and QC1 are When PE is held high, all the outputs are synchronized with the positive edge of the CLKIN clock input. When PE is held low, all the outputs are synchronized with the negative edge of CLKIN. The device has LVTTL outputs with 12mA balanced drive. FEATURES • 3 pairs of programmable skew outputs • Low skew: 200ps same pair, 250ps all outputs • Selectable positive or negative edge synchronization: Excellent for DSP applications • • • • • • • • • • • Synchronous output enable Output frequency: 3.75MHz to 85MHz 2x, 4x, 1/2, and 1/4 output frequencies 3 skew grades 3-level inputs for skew and PLL range control PLL bypass mode External feedback, internal loop filter 12mA balanced drive outputs Available in 28 pin QSOP package Jitter < 200 ps peak-to-peak CLKIN input is 5V tolerant H M CLKIN Ref L QA0 QA1 PLL FB_IN Feedback QB0 QB1 PE FSEL* PLL_BYPASS* SELA[1:0]* SELB[1:0]* SELC [1:0]* 2 2 2 Bank “SKEW” Control QC0 QC1 QD0 QD1 OE * Three-level inputs Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com XRK4993 3.3V PROGRAMMABLE SKEW CLOCK BUFFER REV. 1.0.0 PRODUCT ORDERING INFORMATION PRODUCT NUMBER XRK4993IR-2 XRK4993CR-2 XRK4993IR-5 XRK4993CR-5 XRK4993IR-7 XRK4993CR-7 ACCURACY 250 ps 250 ps 500 ps 500 ps 750 ps 750 ps OPERATING TEMPERATURE RANGE -40°C to +85°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C 0°C to +70°C FIGURE 2. PIN OUT OF THE XRK4993 CLKIN VCCQ FSEL SELC0 SELC1 PE VCCN QD1 QD0 GND QC1 QC0 VCCN FB_IN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 QSOP Top View 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND PLL_BYPASS SELB1 SELB0 OE SELA1 SELA0 VCCN QA0 QA1 GND GND QB0 QB1 TABLE 1: FREQUENCY R ANGE SELECT AND tU CALCULATION [1] fNOM (MHZ) FSEL[2,3] LOW MID HIGH MIN 15 25 40 MAX 35 60 85 tU = 1 / (fNOM X N) WHERE APPROXIMATE FREQUENCY (MHZ) AT WHICH tU N= = 1.0ns 44 26 16 22.7 38.5 62.5 2 XRK4993 REV. 1.0.0 3.3V PROGRAMMABLE SKEW CLOCK BUFFER PIN DESCRIPTIONS PIN NAME CLKIN FB_IN PLL_BYPASS PIN # 1 14 27 TYPE Input Input Threelevel Input Input Reference Clock Input Feedback Input When MID or HIGH, disables PLL (see Special Functions). CLKIN goes to all outputs. Skew Selections (see Control Summary Table) remain in effect. Set LOW for normal operations. Synchronous Output Enable. When HIGH, it stops clock outputs (except QC[1:0]). QC[1:0] may be used as the feedback signal to maintain phase lock. Set OE LOW for normal operation. Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the falling/rising edge of the reference clock. 3-level inputs for selecting 1 of 9 skew taps or frequency functions. DESCRIPTION OE 24 PE SELA0 SELA1 SELB0 SELB1 SELC0 SELC1 FSEL 6 22 23 25 26 4 5 3 Input Threelevel Input Threelevel Input Threelevel Input Threelevel Input Output Selects appropriate oscillator circuit based on anticipated frequency range. (See PLL Programmable Skew Range.) Three output banks of two outputs with programmable skew (QA[1:0], QB[1:0], QC[1:0]). QD[1:0] outputs have fixed zero skew outputs. QA0 QA1 QB0 QB1 QC0 QC1 QD0 QD1 VCCN 20 19 16 15 12 11 9 8 7 13 21 2 10 17 18 28 Output Output Output PWR Power supply for output buffers. VCCQ GND PWR PWR Power supply for phase locked loop and other internal circuitry. Ground. 3 XRK4993 3.3V PROGRAMMABLE SKEW CLOCK BUFFER SKEW SELECT CONTROL The skew select control consists of four independent sections. Each bank has two low-skew, high-fanout drivers (Qx0, Qx1), and two corresponding three-level function select (SELx0, SELx1) inputs. The nine possible output states for each bank as shown in Table 2 as determined by each bank’s select inputs. All timing measurements are made with respect to the CLKIN input assuming that the output connected to the FB_IN input configured for 0 tU operation. TABLE 2: PROGRAMMABLE SKEW CONFIGURATIONS [1] FUNCTION SELECTS SELX1 LOW LOW LOW MID MID MID HIGH HIGH HIGH SELX0 LOW MID HIGH LOW MID HIGH LOW MID HIGH OUTPUT FUNCTIONS QA[1:0], QB[1:0] -4tU -3tU -2tU -1tU 0tU +1tU +2tU +3tU +4tU QC[1:0] Divide by 2 -6tU -4tU -2tU 0tU +2tU +4tU +6tU Divide by 4 REV. 1.0.0 NOTES: 1. For all three-level (three-state) inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry holds an unconnected input to VCC/2. 2. The level to be set on FSEL is determined by the “normal” operating frequency (fNOM) of the PLL. Nominal frequency (fNOM) always appears at QA0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the CLKIN and FB_IN inputs will be fNOM when the output connected to FB_IN is undivided. The frequency of the CLKIN and FB_IN inputs will be fNOM/2 or fNOM/4 when the part is configured for a frequency multiplication. When the FSEL pin is selected HIGH, the CLKIN input must not transition upon power-up until VCC has reached 2.8V. QD[1:0] fixed at zero skew. 3. 4. BYPASS MODE BYPASS mode allows the chip to be used in applications where the relative timing between outputs is maintained but the system clocking is interrupted or at a much lower frequency. An example might be "singlestepping" the system for diagnostics. The PLL_BYPASS pin is normally held at Ground (Low). To accommodate low frequency (below the PLL lock range) or infrequent pulses, the PLL_BYPASS, in conjunction with the FSEL pin (see Table 3) can be used to by-pass the PLL and generate an output sequence for the CLKIN signal. Relative timing as set by the SEL(x)1:0 for the various banks will be maintained. The relative timing includes plus and minus n tu and divide-by (2 or 4) settings. There will be a propagation delay as shown in Table 3. A tu will be approximately 2.5nS with PLL_BYPASS at Mid voltage and 0.4nS in the High state. 4 XRK4993 REV. 1.0.0 3.3V PROGRAMMABLE SKEW CLOCK BUFFER In the PLL_BYPASS mode the PE input can be used to invert the outputs. Thus, for a 20% (High) duty cycle input, all outputs will retain the 20% high condition with PE High. For PE Low, however, they will be 80% High. PE does not effect the duty cycle of the divided outputs. TABLE 3: TYPICAL PROPAGATION DELAY WITH ZERO SKEW SETTING PLL_BYPASS INPUT Mid FSEL INPUT Low or Mid High High Low or Mid High TOTAL PROPAGATION DELAY 52nS 29nS 12nS 10nS SPECIAL FUNCTIONS The following special functions have been implemented in the chip. PE pin: • In Normal operation, PE controls the "alignment" edge of the CLKIN and the FB-IN signals. (All other output signals are aligned to the Feedback). PE=Low, aligns the FB_IN faliing edge to the CLKIN falling edge. PE=High, aligns rising edges. • In the "disabled output mode (see below), the disabled state is forced to the opposite state of PE. This keeps the off condition in a low-noise state. • In PLL_BYPASS mode, PE controls the duty cycle (inversion) of the outputs (see PLL_BYPASS mode above). OE pin: • In Normal mode, OE is used to disable all outputs except QC[1,0]. These are maintained to provide PLL Feedback to keep frequency lock. OE is kept low to enable the outputs and High to disable them. This is a synchronized operation to prevent "partial" clocks When OE goes high, the outputs will go to their disabled level at the end of the next active clock cycle. The level is determined by the state of PE. If PE is high, the output will go low at the end of the cycle and remain there until OE return to a low state. If PE is low, at the end of the next clock high state it will continue to remain high until OE returns low. • If OE is high when PLL_BYPASS is at the Mid level, the PLL is enabled to provide an individual bank output control. In this mode, taking both SEL(x)1 & 0 to the Low state will disable that bank's outputs. FIGURE 3. TYPICAL OUTPUTS WITH FB_IN CONNECTED TO A ZERO-SKEW OUTPUT t0+1tU t0+2tU t0+3tU t0+4tU t0+5tU t0+6tU t0-6tU t0-5tU t0-4tU t0-3tU t0-2tU t0-1tU FB_IN SELA [1:0] SELB [1:0] (N/A) LL LM LH ML MM MH HL HM HH (N/A) (N/A) CLKIN SELC [1:0] -6tU LM -4tU LH -3tU (N/A) -2tU ML -1tU (N/A) 0tU MM +1tU (N/A) +2tU MH +3tU (N/A) +4tU HL +6tU HM LL/HH DIVIDED 5 t0 XRK4993 3.3V PROGRAMMABLE SKEW CLOCK BUFFER REV. 1.0.0 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Storage Temperature Ambient Temperature with Power Applied Supply Voltage to Ground Potential DC Input Volta