SKEW CLOCK BUFFER

www.DataSheet4U.com xr OCTOBER 2005 XRK4991 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER REV. 1.0.1 FUNCTIONAL DESCRIPTION The XRK4991 is a 3.3V High-Speed Low-Voltage Programmable Skew Clock Buffer. It is intended for high-performance computer systems and offers user selectable control over system clock functions to optimize timing. Eight outputs, arranged in four banks, can each drive 50Ω terminated transmission lines while delivering minimal and specified output skews and full-swing Low Voltage TTL logic levels. Each bank (two outputs per bank) can be individually selected for one of nine delay or function configurations through two dedicated tri-level inputs. These outputs are able to lead or lag the CLKIN input reference clock by up to 6 time units from their nominal “zero” skew position. The integrated PLL allows external load and transmission line delay effects to be canceled achieving zero delay capability. Combining the zero delay capability with the selectable output skew functions, output-to-output delays of up to ±12 time units can be created. The XRK4991’s divide functions (divide-by-two and divide-by-four) allow distribution of a low-frequency clock that can be multiplied by two or four at the clock destination. This feature facilitates clock distribution while allowing maximum system clock flexibility. FEATURES • 3.75- to 85-MHz output operation • All output pair skew <100 ps typical • Three skew grades -2 : tSKEW0<250ps -5 : tSKEW0<500ps -7 : tSKEW0<700ps • Selectable output functions Skew adjustments of +/- 6tU (up to 18 ns) Inverted and non-inverted Operation at 1/2 and 1/4 input frequency Operation at 2x and 4x input frequency • Cycle-Cycle Jitter < 25 ps (rms) < 200 ps (pk-pk) • Zero input-to-output delay • 50% duty-cycle outputs • LVTTL outputs drive 50Ω terminated lines • Operates from a single 3.3V supply • 32-pin PLCC package • Green packaging • Lead free lead frame available FIGURE 1. BLOCK DIAGRAM OF THE XRK4991 H M CLKIN Ref L QA0 QA1 PLL FB_IN Feedback QB0 QB1 FSEL* PLL_BYPASS* Bank “SKEW” Control QC0 QC1 SELA[1:0]* SELB[1:0]* SELC[1:0]* SELD[1:0]* * Tri-Level inputs 2 2 2 2 QD0 QD1 Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com XRK4991 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER xr REV. 1.0.1 PRODUCT ORDERING INFORMATION PRODUCT NUMBER XRK4991IJ-2 XRK4991CJ-2 XRK4991IJ-5 XRK4991CJ-5 XRK4991CJ-7 ACCURACY 250 ps 250 ps 500 ps 500 ps 750 ps TEMPERATURE RANGE -40°C to +85°C 0°C to +70°C -40°C to +85°C 0°C to +70°C 0°C to +70°C FIGURE 2. PIN OUT OF THE XRK4991 PLL_BYPASS 31 SELC0 4 SELC1 SELD0 SELD1 VCCQ VCCN QD1 QDO GND GND 5 6 7 8 9 10 11 12 13 14 QC1 3 2 1 32 30 29 28 27 26 SELB0 GND SELA1 SELA0 VCCN QA0 QA1 GND GND XRK4991 SELB1 25 24 23 22 21 20 QB0 CLKIN 17 FB_IN FSEL 15 QC0 16 VCCN 18 VCCN GND VCCQ 19 QB1 2 xr REV. 1.0.1 XRK4991 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER PIN DESCRIPTIONS PIN NAME CLKIN FB_IN FSEL PLL_BYPASS SELA0 SELA1 SELB0 SELB1 SELC0 SELC1 SELD0 SELD1 QA0 QA1 QB0 QB1 QC0 QC1 QD0 QD1 VCCN PIN # 1 17 3 31 26 27 29 30 4 5 6 7 24 23 20 19 15 14 11 10 9 16 18 25 2 8 12 13 21 22 28 32 TYPE I I I I I Reference clock input. PLL’s feedback input. (Normally connected to one of the eight outputs) Tri-level frequency range select. See Table 1 Tri-level select. See PLL_BYPASS section. Tri-level select inputs for Bank A outputs (QA0, QA1). See Table 2. DESCRIPTION I Tri-level select inputs for Bank B outputs (QB0, QB1). See Table 2. I Tri-level select inputs for Bank C outputs (QC0, QC1). See Table 2. I Tri-level select inputs for Bank D outputs (QD0, QD1). See Table 2. O Bank A output pair. See Table 2. O Bank B output pair. See Table 2. O Bank C output pair. See Table 2. O Bank D output pair. See Table 2. PWR Power supply for output drivers. VCCQ GND PWR Power supply for internal circuitry. PWR Ground. 3 XRK4991 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER TABLE 1: FREQUENCY RANGE SELECT AND tU CALCULATION [1] fNOM (MHZ) FSEL[2] LOW MID HIGH[3] MIN 15 25 40 MAX 30 50 85 xr REV. 1.0.1 tU = 1 / (fNOM X N) WHERE APPROXIMATE FREQUENCY (MHZ) AT WHICH tU N= = 1.0ns 44 26 16 22.7 38.5 62.5 SKEW SELECT CONTROL The skew select control consists of four independent banks. Each bank has two low-skew, high-fanout drivers (Qx0, Qx1), and two corresponding tri-level function select (SELx0, SELx1) inputs. The nine possible output states for each bank are shown in Table 2 as determined by each bank’s select inputs. All timing measurements are made with respect to the CLKIN input with the output connected to the FB_IN input configured for 0 tU operation. TABLE 2: PROGRAMMABLE SKEW CONFIGURATIONS [1] FUNCTION SELECT INPUTS SELX1 LOW LOW LOW MID MID MID HIGH HIGH HIGH SELX0 LOW MID HIGH LOW MID HIGH LOW MID HIGH QA[1:0], QB[1:0] -4tU -3tU -2tU -1tU 0tU +1tU +2tU +3tU +4tU OUTPUT FUNCTIONS QC[1:0] ÷2 -6tU -4tU -2tU 0tU +2tU +4tU +6tU ÷4 QD[1:0] ÷2 -6tU -4tU -2tU 0tU +2tU +4tU +6tU Inverted NOTES: 1. For all tri-level (three-state) inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry holds an unconnected input to VCC/2. 2. The level to be set on FSEL is determined by the “normal” operating frequency (fNOM) of the PLL. Nominal frequency (fNOM) always appears at QA0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the CLKIN and FB_IN inputs will be fNOM when the output connected to FB_IN is undivided. The frequency of the CLKIN and FB_IN inputs will be fNOM ÷ 2 or fNOM ÷ 4 when the part is configured for a frequency multiplication. 3. When the FSEL pin is selected HIGH, the CLKIN input must not transition upon power-up until VCC has reached 2.8V. 4 xr REV. 1.0.1 XRK4991 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER FIGURE 3. TYPICAL OUTPUTS WITH FB_IN CONNECTED TO A ZERO-SKEW OUTPUT t0+1tU t0+2tU t0+3tU t0+4tU t0+5tU t0+6tU t0-6tU t0-5tU t0-4tU t0-3tU t0-2tU t0-1tU FB_IN SELA[1:0] SELB[1:0] (N/A) LL LM LH ML MM MH HL HM HH (N/A) (N/A) (N/A) CLKIN SELC[1:0] SELD[1:0] -6tU LM -4tU LH -3tU (N/A) -2tU ML -1tU (N/A) 0tU MM +1tU (N/A) +2tU MH +3tU (N/A) +4tU HL +6tU HM LL/HH DIVIDED HH(D) INVERT PLL_BYPASS The PLL_BYPASS input is a tri-level input. In normal system operation, this pin is connected to ground. In normal operation (tied LOW) all outputs will function based only on the connection of their own function select inputs (SELx[1:0]) and the waveform characteristics of the PLL. If the PLL_BYPASS input is forced to its MID or HIGH state the device will operate in PLL bypass mode, with the phase locked loop disconnected, and CLKIN waveforms will directly control all outputs. Relative output to output timing is controlled by the SELx[1:0], the same as in normal mode. 5 t0 XRK4991 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER xr REV. 1.0.1 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Storage Temperature Ambient Temperature with Power Applied Supply Voltage to Ground Potential DC Input Voltage Output Current into Outputs (LOW) Static Discharge Voltage (per MIL-STD-883, Method 3015) Latch-Up Current. –65°C to +150°C –55°C to +125°C –0.5V to +7.0V –0.5V to +7.0V 64 mA >3000V >200 mA OPERATING RANGE RANGE Industrial Commercial AMBIENT TEMPERATURE -40°C to +85°C 0°C to +70°C VCC 3.3 + 10% 3.3 + 10% ELECTRICAL CHARACTERISTICS OVER THE 3.3V + 10% OPERATING RANGE SYMBOL VOH VOL VIH VIL VIHH DESCRIPTION Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage tri-level Input HIGH Voltage (FSEL, SELx[1:0], Test) [4] VIMM tri-level Input MID Voltage (FSEL, SELx[1:0], Test) VILL [4] MIN 2.4 MAX UNIT V CONDITION VCC = Min., IOH = -18mA VCC = Min., IOL = 35mA (CLKIN and FB_IN inputs only) Min. < VCC < Max. 0.45 2.0 -0.5 0.87*VCC VCC 0.8 VCC V V V V 0.47*VCC 0.53 * VCC V Min. < VCC < Max. tri-level Input LOW Voltage (FSEL, SELx[1:0], Test) [4] 0.0 0.13 * VCC V Min. < VCC < Max. IIH IIL IIHH IIMM IILL Input HIGH Leakage Current (CLKIN and FB_IN inputs only) Input LOW Leakage Current (CLKIN and FB_IN inputs only) Input HIGH Current (FSEL, SELx[1:0], Test) Input MID Current (FSEL, SELx[1:0], Test) Input LOW Current (FSEL, SELx[1:0], Test) -50 -20 20 µΑ µΑ VCC = Max., VIN = Max. VCC = Max., VIN = 0.4V VIN = VCC VIN = VCC/2 VIN = GND 200 µΑ µA µA 50 -200 6 xr REV. 1.0.1 XRK4991 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER ELECTRICAL CHARACTERISTICS OVER THE 3.3V + 10% OPERATING RANGE SYMBOL IOS DESCRIPTION Short Circuit Current [5] MIN MAX -200 UNIT mA CONDITION VCC = Max, VOUT = GND (25° only) ICCQ Operating Current Used by Internal Circuitry Com’l Ind 95 100 19 mA mA VCCN = VCCQ = Max., All Inputs Selects Open VCCN = VCCQ = Max., IOUT = 0 mA Inputs Selects Open, fMAX PD Power Dissipation per Output Pair [7] 104 mW VCCN = VCCQ = Max., IOUT = 0 mA Input Selects Open, fMAX ICCN Output Buffer Current per Output Pair [6] CAPACITANCE[8] SYMBOL CIN Input Capacitance DESCRIPTION MAX. 10 UNIT pF CONDITION TA = 25°C, f=1MHz, VCC=3.3V NOTES: 4. These inputs are normally wired to VCC, GND or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before all data sheet limits are achieved. 5. XRK4991 should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. 6. Total output current per output pair can be approximated by the following expression that includes device current plus load current: XRK4991: ICCN = {(4+0.11F) +