www.DataSheet4U.com
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FEBRUARY 2005
PRELIMINARY
XRK4991A
REV. P1.0.2
3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
at the clock destination. This feature minimizes clock distribution difficulty while allowing maximum system clock speed and flexibility. FEATURES
FUNCTIONAL DESCRIPTION
The XRK4991A 3.3V High-Speed Low-Voltage Programmable Skew Clock Buffer offers user selectable control over system clock functions to optimize the timing of high-performance computer systems. Eight individual drivers, arranged as four pairs of user-controllable outputs, can each drive terminated transmission lines with impedances as low as 50Ω while delivering minimal and specified output skews and full-swing logic levels (LVTTL). Each output can be hardwired to one of nine delay or function configurations. Delay increments of 0.7 to 1.5 ns are determined by the operating frequency with outputs able to skew up to ±6 time units from their nominal “zero” skew position. The completely integrated PLL allows external load and transmission line delay effects to be canceled. When this “zero delay” capability is combined with the selectable output skew functions, the user can create output-tooutput delays of up to ±12 time units. Divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. When combined with the internal PLL, these divide functions allow distribution of a lowfrequency clock that can be multiplied by two or four FIGURE 1. BLOCK DIAGRAM OF THE XRK4991A
TEST PE FB_IN PHASE CLKIN FSEL SELD0 SELD1 Select Inputs SELC0 SELC1 SELB0 SELB1 SELA0 SELA1
FREQ DET FILTER
• Ref input is 5V tolerant • 3 pairs of programmable skew outputs • Low skew: 200ps same pair, 250ps all outputs • Selectable positive or negative edge
synchronization: Excellent for DSP applications
• Synchronous output enable • Output frequency: 3.75MHz to 85MHz • 2x, 4x, 1/2, and 1/4 outputs • 2 skew grades • 3-level inputs for skew and PLL range control • PLL bypass for DC testing • External feedback, internal loop filter • 12mA balanced drive outputs • 32-pin PLCC package • Jitter < 200 ps peak-to-peak (< 25 ps RMS) • Green packaging
VCO AND TIME UNIT GENERATOR
0E QD0 QD1
SKEW SELECT
QC0 QC1 QB0
MATRIX
QB1 QA0 QA1
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRK4991A PRELIMINARY 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
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REV. P1.0.2
PRODUCT ORDERING INFORMATION
PRODUCT NUMBER XRK4991AIJ-5 XRK4991ACJ-5 XRK4991ACJ-7 XRK4991AIJ-7 ACCURACY 500 ps 500 ps 750 ps 750 ps OPERATING TEMPERATURE RANGE -40°C to +85°C 0°C to +70°C 0°C to +70°C -40°C to +85°C
FIGURE 2. PIN OUT OF THE XRK4991
SELC0
4 SELC1 SELD0 SELD1 PE VCCN QD1 QDO GND GND 5 6 7 8 9 10 11 12 13 14 QD1
3
2
1
32
31
SELB1 30 29 28 27 26 SELB0 OE SELA1 1F0 VCCN QA0 QA1 GND GND 25 24 23 22 21 20 QB0
CLKIN
XRK4991A
15 QC0
16 VCCN
17 FB_IN
18 VCCN
2
QB1
TEST 19
FSEL
GND
VCCQ
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REV. P1.0.2
PRELIMINARY XRK4991A 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
PIN DESCRIPTIONS
PIN NAME CLKIN FB_IN FSEL SELA0 SELA1 SELB0 SELB1 SELC0 SELC1 SELD0 SELD1 TEST OE PIN # 1 17 3 26 27 29 30 4 5 7 1 31 28 TYPE I I I I I I I I I DESCRIPTION Reference frequency input. This input supplies the frequency and timing against which all functional variation is measured. PLL feedback input (typically connected to one of the eight outputs). Three-level frequency range select. Set Table 2. Three-level function selects inputs for output pair 1 (QA0, QA0]). Table 3. Three-level function selects inputs for output pair 2 (QB0, QB1). Table 3. Three-level function selects inputs for output pair 3 (QC0, QC1). See Table 3. Three-level function selects inputs for output pair 4 (QD0, QD1). See Table 3. Three-level select. See test mode section under the block diagram descriptions. Synchronous Output Enable. When HIGH, it stops clock outputs (except QC[1:0]) in a "Low" state - QC[1:0] may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and OE is "High", the nF[1:0] pins act as output disable controls for individual banks when nF[1:0] = LL. Set OE "Low" for normal operation. Selectable positive or negative edge control. When "Low"/"High" the outputs are synchronized with the negative/positive edge of the reference clock. Output pair 1. See Table 2. Output pair 2. See Table 2. Output pair 3. See Table 2. Output pair 4. See Table 2. Power supply for output drivers.
PE QA0 QA1 QB0 QB1 QC0 QC1 QD0 QD1 VCCN
8 24 23 20 19 15 14 11 10 9 16 18 25 2 12 13 21 22 32
I O O O O PWR
VCCQ GND
PWR PWR
Power supply for internal circuitry. Ground.
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XRK4991A PRELIMINARY 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER EXTERNAL FEEDBACK
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REV. P1.0.2
By providing external feedback, the XRK4991A gives users flexibility with regard to skew adjustment. The FB_IN signal is compared with the input CLKIN signal at the phase detector in order to drive the VCO. Phase differences cause the VCO to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes. TABLE 1: PLL PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE
FSEL = LOW Timing Unit Calculation (tU) VCO Frequency Range (FNOM) (1,2) Skew Adjustment Range (3) Max Adjustment: 1/(44 x FNOM) 15 to 35MHz FSEL = MID 1/(26 x FNOM) 25 to 60MHz FSEL = HIGH 1/(16 x FNOM) 40 to 100MHz COMMENTS
+9.09ns +49° +14%
+9.23ns +83° +23%
+9.38ns +135° +37%
ns Phase Degrees % of Cycle Time
Example 1, FNOM = 15MHz Example 2, FNOM = 25MHz Example 3, FNOM = 30MHz Example 4, FNOM = 40MHz Example 5, FNOM = 50MHz Example 6, FNOM = 80MHz NOTES: 1.
tU = 1.52ns tU = 0.91ns tU = 0.76ns tU = 1.54ns tU = 1.28ns tU = 0.96ns tU = 0.77ns tU = 1.56ns tU = 1.25ns tU = 0.78ns
The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. Selecting the appropriate FSEL value based on input frequency range allows the PLL to operate in its ‘sweet spot’ where jitter is lowest. The level to be set on FSEL is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at QA[1:0], QB[1:0] and the higher outputs when they are operated in their undivided modes. The frequency appearing at the CLKIN and FB_IN inputs will be the same as the VCO when the output connected to FB_IN is undivided. The frequency of the CLKIN and FB_IN inputs will be 1/2 or 1/4 the VCO frequency when the part is configured for a frequency multiplication by using a divided output as the FB_IN input. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example if a 4tU skewed output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range applies to output pairs 3 and 4 where ± 6tU skew adjustment is possible and at the lowest FNOM value.
2.
3.
4
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REV. P1.0.2
PRELIMINARY XRK4991A 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
TABLE 2: FREQUENCY RANGE SELECT AND tU CALCULATION [1] fNOM (MHZ) tU = 1 / fNOM X N
MAX 30 50 85
WHERE
APPROXIMATE FREQUENCY (MHZ) AT
WHICH tU
FSEL[2,3] LOW MID HIGH
MIN 15 25 40
N=
= 1.0ns
44 26 16
22.7 38.5 62.5
SKEW SELECT MATRIX The skew select matrix is comprised of four independent sections. Each section has two low-skew, high-fanout drivers (Qx[0:1]), and two corresponding three-level function select (SELx[0:1]) inputs. Table 2 below shows the nine possible output functions for each section as determined by the function select inputs. All times are measured with respect to the CLKIN input assuming that the output connected to the FB_IN input has 0tU selected. TABLE 3: PROGRAMMABLE SKEW CONFIGURATIONS [1]
FUNCTION SELECTS SELX1 LOW LOW LOW MID MID MID HIGH HIGH HIGH SELX0 LOW MID HIGH LOW MID HIGH LOW MID HIGH QA[1:0], QB[1:0] -4tU -3tU -2tU -1tU 0tU +1tU +2tU +3tU +4tU OUTPUT FUNCTIONS QC[1:0] Divide by 2 -6tU -4tU -2tU 0tU +2tU +4tU +6tU Divide by 4 QD[1:0] Divide by 2 -6tU -4tU -2tU 0tU +2tU +4tU +6tU Inverted
NOTES: 1. For all three-state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry holds an unconnected input to VCC/2. 2. The level to be set on FSEL is determined by the “normal” operating frequency (fNOM) of the VCO and Time Unit Generator (see Logic Block Diagram). Nominal frequency (fNOM) always appears at QA0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the CLKIN and FB_IN inputs will be fNOM when the output connected to FB_IN is undivided. The frequency of the CLKIN and FB_IN inputs will be fNOM/2 or fNOM/4 when the part is configured for a frequency multiplication by using a divided output as the FB_IN input. When the FSEL pin is selected HIGH, the CLKIN input must not transition upon power-up until VCC has reached 2.8V.
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XRK4991A PRELIMINARY 3.3V HIGH-SPEED (85 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER FIGURE 3. TYPICAL OUTPUTS WITH FB_IN CONNECTED TO A ZERO-SKEW OUTPUT [4]
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REV. P1.0.2
t0+1tU
t0+2tU
t0+3tU
t0+4tU
t0+5tU
FB_IN SELA-QA[1:0] SELC-QC[1:0] CLKIN SELB-QB[1:0] SELD-QD[1:0] -6tU (N/A) LM -4tU LL LH -3tU LM (N/A) -2tU LH ML -1tU ML (N/A) 0tU MM MM +1tU MH (N/A) +2tU HL MH +3tU HM (N/A) +4tU HH HL +6tU (N/A) HM (N/A) LL/HH DIVIDED (N/A) HH INVERT
NOTES: 4. FB_IN connected to an output selected for "zero" skew (i.e. SELx1 = SELx0 = MID).
TEST MODE The TEST input is a three-level input.
