3.3V LOW SKEW PLL CLOCK DRIVER

www.DataSheet4U.com JULY 2006 XRK39910 3.3V LOW SKEW PLL CLOCK DRIVER REV. 1.0.0 FUNCTIONAL DESCRIPTION The XRK39910 is a high fanout phase locked-loop clock driver intended for high performance computing and data-communications applications. It has eight zero delay LVTTL outputs. When the OE pin is held low, all the outputs are synchronously enabled. However, if OE is held high, all the outputs except Q2 and Q3 are synchronously disabled. Furthermore, when the PE is held high, all the outputs are synchronized with the positive edge of the CLKIN. When PE is held low, all the outputs are synchronized with the negative edge of CLKIN. The FB_IN signal is compared with the input CLKIN signal at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes. FEATURES • • • • • • • • • • • • Eight zero delay outputs 12mA balanced drive outputs Output frequency: 15MHz to 85MHz <250ps of output to output skew Low Jitter: <200ps peak-to-peak 3 skew grades External feedback, internal loop filter Selectable positive synchronization or negative edge Synchronous output enable 3-level inputs for PLL range control PLL bypass for DC testing Available in SOIC package FIGURE 2. PIN C ONFIGURATION CLKIN VDDPLL FSEL nc PE 1 2 3 4 5 6 24 23 22 21 20 19 GND Bypass nc OE VDD Q7 Q6 GND Q5 Q4 VDD FB_IN FIGURE 1. FUNCTIONAL BLOCK DIAGRAM Q0 VDD Q0 Q1 XRK39910 7 8 9 10 11 12 18 17 16 15 14 13 H Q1 CLKIN M Ref VCO L Q2 PLL Q3 FB_IN Feedback GND Q2 Q3 VDD Q4 FSEL* PE Bypass* Q5 Q6 Q7 OE * Tri-Level inputs Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com XRK39910 3.3V LOW SKEW PLL CLOCK DRIVER TABLE 1: ORDERING INFORMATION PRODUCT N UMBER XRK39910CD-2 XRK39910ID-2 XRK39910CD-5 XRK39910ID-5 XRK39910CD-7 XRK39910ID-7 ACCURACY 250ps 250ps 500ps 500ps 750ps 750ps TEMP R ANGE 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C REV. 1.0.0 TABLE 2: ABSOLUTE MAXIMUM RATINGS(1) SYMBOL D ESCRIPTION Supply Voltage to Ground VI DC Input Voltage CLKIN Input Voltage Maximum Power Dissipation (TA = 85°C) TSTG Storage Temperature MAX -0.5 to +7 -0.5 to VDD+0.5 -0.5 to +5.5 530 -65 to +150 UNIT V V V mW °C NOTE: (1) Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability. TABLE 3: CAPACITANCE (TA= +25 °C, f= 1MH Z, VIN= 0V) PARAMETER CIN DESCRIPTION Input Capacitance TYP 5 MAX 7 UNIT pF NOTE: Capacitance applies to all inputs except BYPASS and FSEL. It is characterized but not production tested . TABLE 4: PIN D ESCRIPTIONS PIN NAME CLKIN VDDPLL FSEL(1,3) PIN N UMBER 1 2 3 TYPE IN Reference Clock Input DESCRIPTION PWR Power supply for phase locked loop and other internal circuitry. IN Frequency range select: FSEL = GND:15 to 35MHz FSEL = MID (or open): 25 to 60MHz FSEL = VDD: 40 to 85MHz PE VDD 5 6,12,14,20 IN Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference clock. PWR Power supply for output buffers. 2 XRK39910 REV. 1.0.0 3.3V LOW SKEW PLL CLOCK DRIVER TABLE 4: PIN D ESCRIPTIONS PIN NAME Q 0 - Q7 GND FB_IN OE(2) PIN N UMBER 7,8,10,11, 15,16,18,19 9,17,24 13 21 TYPE OUT Eight clock output. DESCRIPTION PWR Ground. IN IN Feedback Input Synchronous Output Enable. When HIGH, it stops clock outputs (except Q2 and Q3) in a LOW state - Q2 and Q 3 may be used as the feedback signal to maintain phase lock. Set OE LOW for normal operation. When MID or HIGH, disable PLL (except for conditions of Note 2). CLKIN goes to all outputs. Set LOW for normal operations. BYPASS(1,2) 23 IN NOTE: 1. 2. 3. Tri-Level Input When BYPASS = MID and OE = HIGH, PLL remains active. This input is wired to VDD, GND, or unconnected. Default is MID level. If it is switched in the real time mode, the outputs may glitch, and the PLL may require an additional lock time before all data sheet limits are achieved. TABLE 5: RECOMMENDED OPERATING RANGE XRK39910-2, -5, -7 (INDUSTRIAL) MIN. VDD TA Power Supply Voltage Ambient Operating Temperature 3 -40 MAX. 3.6 +85 XRK39910-2, -5, -7 (COMMERCIAL) MIN. 3 0 MAX. 3.6 +70 V °C SYMBOL DESCRIPTION UNIT TABLE 6: DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE SYMBOL VIH PARAMETER Input HIGH Voltage C ONDITIONS Guranteed Logic HIGH (CLKIN, FB_IN, OE, PE Inputs Only) Guaranteed Logic LOW (CLKIN, FB_IN, OE, PE Inputs Only) 3-Level Inputs Only (FSEL, BYPASS) 3-Level Inputs Only (FSEL, BYPASS) 3-Level Inputs Only (FSEL, BYPASS) VIN = VDD or GND VDD = Max. VDD-0.6 MIN. 2 MAX. UNIT V VIL Input LOW Voltage 0.8 V VIHH Input HIGH Voltage (1) Input MID Voltage (1) Input LOW Voltage (1) Input Leakage Current (CLKIN, FB_IN Inputs Only) V VIMM VDD/2-0.3 VDD/2+0.3 V VILL 0.6 V μA IIN +5 3 XRK39910 3.3V LOW SKEW PLL CLOCK DRIVER TABLE 6: DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE SYMBOL I3 PARAMETER 3-Level Input DC Current (BYPASS, FSEL) VIN = VDD VIN = VDD/2 VIN = GND IPU IPD VOH VOL Input Pull-Up current (PE) Input Pull-Down Current (OE) Output HIGH Voltage Output LOW Voltage C ONDITIONS HIGH Level MID Level LOW Level MIN. MAX. +400 +200 +400 +100 +100 2.4 0.55 μA μA V V UNIT μA REV. 1.0.0 VDD = Max., VIN = GND VDD= Max., VIN = VDD VDD = Min., IOH = -12mA VDD = Min., IOL = 12mA NOTE: (1) These inputs are normally wired to V DD, GND, or unconnected. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched, the function and timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved. TABLE 7: POWER SUPPLY CHARACTERISTICS SYMBOL IDDQ PARAMETER Quiescent Power Supply Current TEST C ONDITIONS(1) VDD=Max., BYPASS=MID, CLKIN=LOW VDD/PE=LOW, OE=LOW, All outputs unloaded VDD=3.3V, FREF=25MHz, C L=160pF(1) VDD=3.3V, FREF=33MHz, C L=160pF(1) VDD=3.3V, FREF=66MHz, C L=160pF(1) NOTE: (1) For eight outputs, each loaded with 20pF. TYP. 8 MAX. 25 UNIT mA ITOT Total Power Supply Current 34 42 76 mA TABLE 8: INPUT TIMING R EQUIREMENTS SYMBOL tR, tF tPWC DH Ref DESCRIPTION(1) Maximum input rise and fall times, 0.8V to 2V Input clock pulse, HIGH or LOW Input duty cycle Reference Clock Input 3 10 15 90 85 M IN. MAX. 10 UNIT ns/V ns % MHz NOTE: (1) Where pulse width implied by D H is less than tPWC limit, tPWC limit applies. 4 XRK39910 REV. 1.0.0 3.3V LOW SKEW PLL CLOCK DRIVER TABLE 9: SWITCHING CHARACTERISTICS OVER OPERATING RANGE XRK39910-2 SYMBOL FREF PARAMETER MIN CLKIN Frequency Range FSEL = LOW FSEL = MED FSEL = HIGH tRPWH tRPWL tSKEW tDEV tPD tODCV tORISE tOFALL tLOCK tJR CLKIN Pulse Width HIGH CLKIN Pulse Width LOW Output Skew (All Outputs) [1, 3, 4] Device-to-Device Skew [1, 2, 5] CLKIN Input to FB_IN Propagation Delay [1, 7] -0.25 Output Duty Cycle Variation from 50% [1] Output Rise Time [1] Output Fall Time [1] PLL Lock Time [1,6] Cycle-to-Cycle Output Jitter [1] RMS Peak-to-Peak -1.2 0.15 0.15 0 0 1 1 15 25 40 3 3 0.1 0.25 0.75 0.25 1.2 1.2 1.2 0.5 25 200 -0.5 -1.2 0.15 0.15 0 0 1 1 TYP M AX 35 60 85 MIN 15 25 40 3 3 0.25 0.5 1.25 0.5 1.2 1.5 1.5 0.5 25 200 -0.7 -1.2 0.15 0.15 0 0 1.5 1.5 TYP MAX 35 60 85 MIN 15 25 40 3 3 0.3 0.75 1.65 0.7 1.2 2.5 2.5 0.5 25 200 TYP MAX 35 60 85 ns ns ns ns ns ns ns ns ms ps MHz XRK39910-5 XRK39910-7 UNIT NOTES: 1. 2. 3. 4. 5. 6. All timing and jitter tolerances apply for FNOM > 25MHz. Skew is the time between the earliest and the latest output transition among all outputs with the specified load. tSKEW is the skew between all outputs. See AC TEST LOADS. For XRK39910-2 tSKEW is measured with CL = 0pF; for CL = 20pF, tSKEW = 0.35ns Max. tDEV is the output-to-output skew between any two devices operating under the same conditions. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at CLKIN or FB_IN until tPD is within specified limits. tPD is measured with CLKIN input rise and fall times (from 0.8V to 2V ) of 1ns. 7. 5 XRK39910 3.3V LOW SKEW PLL CLOCK DRIVER FIGURE 3. AC TIMING D IAGRAM (PE= HIGH TIMING) tREF tRPWH CLKIN tPD FB_IN tJR Qx output tODCV tODCV tRPWL REV. 1.0.0 tSKEW Other Qx output tSKEW FIGURE 4. AC TIMING D IAGRAM (PE= LOW TIMING) tREF CLKIN tPD FB_IN tJR Qx output tODCV tODCV tRPWH tRPWL tSKEW Other Qx output tSKEW NOTE: Skew: The time between the earliest and the latest output transition among all outputs when all are loaded with 20pF and terminated with 75Ω to VDD/2. tDEV: The output-to-output skew between any two devices operating under the same conditions (VDD, ambient temperature, air flow, etc.). tODCV: The deviation of the output from a 50% duty cycle. tORISE and tOFALL are measured between 0.8V and 2V. tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VDD is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at CLKIN or FB_IN until tPD is within specified limits. 6 XRK39910 REV. 1.0.0 3.3V LOW SKEW PLL CLOCK DRIVER FIGURE 5. AC TEST LOADS AND WAVEFORMS V DD 150Ω Output 150Ω 20pF AC Test Loads <1ns 3.0V 2.0V Vth = 1.5V 0.8V 0V LVTTL