3.3V ZERO DELAY BUFFER

www.DataSheet4U.com MAY 2006 PRELIMINARY XRK32308 3.3V ZERO DELAY BUFFER REV. P1.0.2 GENERAL DESCRIPTION FUNCTIONAL DESCRIPTION XRK32308 is a 3.3V Zero Delay Buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback is required to be driven into the FB pin, and can be obtained from one of the outputs. The input-to-output skew is guaranteed to be less than 350 ps, and output-to-output skew is guaranteed to be less than 200 ps. XRK32308 has two banks of four outputs each. These can be controlled by the Select inputs as shown in Table 2, “Select Input Decoding,” on page 2. If all output clocks are not required, Bank B can be three-stated. The select inputs also allow the input clock to be directly applied to the output for chip and system testing purposes. Multiple XRK32308 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps. XRK32308 devices are available in five different configurations, as shown in Table 3, “Available XRK32308 Configurations,” on page 3. The XRK32308–1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The XRK32308–1H is the high-drive version of the – 1. Rise and fall times on this device are faster. The XRK32308–2 allows the user to obtain 1X, and 2X or X/2 depending on which Bank sources the FB signal. The XRK32308–3 allows the user to obtain 4X and 2X frequencies or 1X and 2X. The XRK32308–4 enables the user to obtain 2X clocks on all outputs. The XRK32308–5H is a high-drive version with REF/ 2 on both banks. FEATURES • Zero input-output propagation delay, adjustable by capacitive load on FB input • Multiple configurations, see “Available XRK32308 Configurations” table • Multiple low-skew outputs • Two banks of four outputs, three-stateable by two select inputs • 10-MHz to 120-MHz operating range • 75ps typical cycle-to-cycle jitter (15pF, 66MHz) • Space-saving 16-pin 150-mil SOIC package or 16pin TSSOP • 3.3V operation • Industrial and commercial temperature available FIGURE 1. BLOCK DIAGRAM AND PIN CONFIGURATION OF THE XRK32308 /2 PLL REF /2 Extra Divider (-3, -4) Extra Divider (-5H) S2 S1 MUX FB QA0 QA1 QA2 QA3 REF QA0 QA1 VDD GND QB0 QB1 S2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 FB QA3 QA2 VDD GND QB3 QB2 S1 Select Input Decoding /2 QB0 QB1 Extra Divider (-2, -3) QB2 QB3 Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com XRK32308 3.3V ZERO DELAY BUFFER PRELIMINARY REV. P1.0.2 TABLE 1: PIN D ESCRIPTION PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 REF[1] QA0[2] QA1[2] VDD GND QB0[2] QB1[2] S2[3] S1[3] QB2[2] QB3[2] GND VDD QA2[2] QA3[2] FB SIGNAL Input reference frequency Clock output, Bank A Clock output, Bank A 3.3V supply Ground Clock output, Bank B Clock output, Bank B Select input, bit 2 Select input, bit 1 Clock output, Bank B Clock output, Bank B Ground 3.3V supply Clock output, Bank A Clock output, Bank A PLL feedback input D ESCRIPTION TABLE 2: SELECT INPUT D ECODING S2 0 0 1 1 NOTES: 1. 2. 3. 4. Weak pull-down. Weak pull-down on all outputs. Weak pull-ups on these inputs. Outputs inverted on XRK32308–2 and XRK32308–3 in bypass mode, S2 = 1 and S1 = 0. S1 0 1 0 1 QA0-QA3 Three-State Driven Driven[4] Driven QB0-QB3 Three-State Three-State Driven[4] Driven OUTPUT SOURCE PLL PLL Reference PLL 2 PRELIMINARY REV. P1.0.2 XRK32308 3.3V ZERO DELAY BUFFER TABLE 3: AVAILABLE XRK32308 CONFIGURATIONS DEVICE XRK32308-1 XRK32308-1H XRK32308-2 XRK32308-2 XRK32308-3 XRK32308-3 XRK32308-4 XRK32308-5H NOTES: 5. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the XRK32308–2. FEEDBACK FROM Bank A or Bank B Bank A or Bank B Bank A Bank B Bank A Bank B Bank A or Bank B Bank A or Bank B BANK A FREQUENCY Reference Reference Reference 2 X Reference 2 X Reference 4 X Reference 2 X Reference Reference/2 BANK B FREQUENCY Reference Reference Reference/2 Reference Reference or Reference[5] 2 X Reference 2 X Reference Reference/2 ZERO DELAY AND SKEW CONTROL FIGURE 2. REF INPUT TO QAX/QB X DELAY VS DIFFERENCE IN LOADING BETWEEN FB AND QAX/QBX PINS 1500 1000 REF Input to QAx/QBx Delay (ps) 500 0 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 -500 -1000 -1500 Output Load Difference: FB Load - QAx/QBx Load (pF) Note: Target only, actual characterization curve may be slightly different. To close the feedback loop of the XRK32308, the FB pin can be driven from any of the eight available output pins. The output driving the FB pin will be driving a total load of 7 pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input-output delay. This is shown in the graph above. For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay adjustments are required, use the above graph to calculate loading differences between the feedback output and remaining outputs. For zero output-output skew, be sure to load outputs equally. 3 XRK32308 3.3V ZERO DELAY BUFFER PRELIMINARY REV. P1.0.2 TABLE 4: ABSOLUTE MAXIMUM RATINGS Supply Voltage to Ground Potential DC Input Voltage (Except Ref) DC Input Voltage REF Storage Temperature Junction Temperature Static Discharge Voltage (per MIL-STD-883, Method 3015) -0.5V to +7.0V -0.5V to V DD +0.5V -0.5 to 7V -65°C to +150°C 150°C >2000V TABLE 5: OPERATING CONDITIONS FOR XRK32308 COMMERCIAL TEMPERATURE DEVICES PARAMETER VDD TA CL Load Capacitance, from 100MHz to 120MHz CIN tPU Input Capacitance[6] Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 15 7 50 pF pF ms Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100MHz DESCRIPTION MIN 3.0 0 MAX 3.6 70 30 UNIT V °C pF NOTES: 6. Applies to both Ref Clock and FB. TABLE 6: ELECTRICAL CHARACTERISTICS FOR XRK32308 COMMERCIAL TEMPERATURE D EVICES PARAMETER VIL VIH IIL IIH VOL DESCRIPTION Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage[7] VIN=0V VIN=VDD IOL= 8mA (-1, -2, -3, -4) IOL= 12mA (-1H, -5H) VOH Output High Voltage[7] IOH= -8mA (-1, -2, -3, -4) IOH= -12mA (-1H, -5H) 2.4 V TEST CONDITIONS MIN 2.0 M AX 0.8 50.0 100.0 0.4 UNIT V V µA µA V 4 PRELIMINARY REV. P1.0.2 XRK32308 3.3V ZERO DELAY BUFFER TABLE 6: ELECTRICAL CHARACTERISTICS FOR XRK32308 COMMERCIAL TEMPERATURE DEVICES PARAMETER DESCRIPTION TEST CONDITIONS Unloaded outputs, 100-MHz REF, Select inputs at VDD or GND MIN M AX 45.0 70 (-1H, -5H) 32.0 18.0 UNIT mA mA mA mA IDD Supply Current Unloaded outputs, 66-MHz REF (-1, -2, -3, -4) Unloaded outputs, 33-MHz REF (-1, -2, -3, -4) NOTES: 7. Parameter is guaranteed by design and characterization. Not 100% tested in production. TABLE 7: SWITCHING CHARACTERISTICS FOR XRK32308 COMMERCIAL TEMPERATURE DEVICES[8] PARAMETER NAME TEST CONDITIONS 30-pF load, All devices t1 Output Frequency 20-pF load, -1H, -5H devices[9] 15-pF load, -1, -2, -3, -4 devices Measured at 1.4V, FOUT=66.66MHz 30-pF load Measured at 1.4V, FOUT<50.0MHz 15-pF load Measured between 0.8V and 2.0V, 30-pF load Measured between 0.8V and 2.0V, 15-pF load Measured between 0.8V and 2.0V, 30-pF load Measured between 0.8V and 2.0V, 30-pF load Measured between 0.8V and 2.0V, 15-pF load Measured between 0.8V and 2.0V, 30-pF load MIN 10 10 10 40.0 TYP 50.0 MAX 100 120 120 60.0 UNIT MHz MHz MHz % DC Duty Cycle = t2 ÷ t1 (-1, -2, -3, -4, -1H, -5H) [7] 45.0 50.0 55.0 % - - 2.20 1.50 1.50 ns ns ns Rise (-1, -2, -3, -4) t3 Rise Time[7] (-1H, -5H) Time[7] - - 2.20 1.50 1.25 ns ns ns Fall Time (-1, -2, -3, -4) t4 Fall Time[7] (-1H, -5H) [7] 5 XRK32308 3.3V ZERO DELAY BUFFER PRELIMINARY REV. P1.0.2 TABLE 7: SWITCHING CHARACTERISTICS FOR XRK32308 COMMERCIAL TEMPERATURE DEVICES[8] PARAMETER NAME TEST CONDITIONS MIN TYP MAX 200 UNIT ps Output to Output Skew on All outputs equally loaded same Bank (-1, -2, -3, -4)[7] Output to Output Skew (-1H, -5H)[7] t5 Output Bank A to Output Bank B Skew (-1, -4, -5H) Output Bank A to Output Bank B Skew (-2, -3) t6 t7 t8 FB Rising Edge[7] Device to Device Skew[7] Output Slew Rate[7] Measured at VDD/2 on the FB pins of devices Measured between 0.8V and 2.0V on -1H, -5H device using Test Circuit #2 Measured at 66.67MHz, loaded outputs, 15-pF load Cycle to Cycle Jitter[7] (-1, -1H, -4, -5H) tJ Measured at 66.67MHz, loaded outputs, 30-pF load Measured at 120MHz, loaded outputs, 15-pF load Measured at 66.67MHz, loaded outputs, 30-pF load Measured at 66.67MHz, loaded outputs, 15-pF load Stable power suppy, valid clock presented on REF and FB pins All outputs equally loaded - - 200 ps All outputs equally loaded - - 200 ps All outputs equally loaded - - 400 ps Delay, REF Rising Edge to Measured at VDD/2 - 0 +250 ps - 0 700 ps 1 - 75 200 200 100 400 400 1.0 V/ns ps ps ps ps ps ms Cycle to Cycle (-2, -3) Jitter[7] tLOCK PLL Lock Time[7] NOTES: 8. 9. All parameters are specified with loaded outputs. XRK32308 has maximum input frequency of 120MHz and maximum output of 66.67MHz. 6 PRELIMINARY REV. P1.0.2 XRK32308 3.3V ZERO DELAY BUFFER TABLE 8: OPERATING C ONDITIONS FOR XRK32308 INDUSTRIAL TEMPERATURE DEVICES PARAMETER VDD TA CL Load Capacitance, from 100MHz to 120MHz CIN tPU Input Capacitance[6] Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 15 7 50 pF pF ms Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance, below 100MHz DESCRIPTION MIN 3.0 -40 MAX 3.6 85 30 UNIT V °C pF TABLE 9: ELECTRICAL CHAR