16-Bit Linear CIS/CCD Sensor Signal Processor

www.DataSheet4U.com XRD9825 16-Bit Linear CIS/CCD Sensor Signal Processor with Serial Control May 2000-3 FEATURES · · · · · · · · · · 16-Bit Resolution One-channel 12MSPS Pixel Rate Triple-channel 4MSPS Pixel Rate 6-Bit Programmable Gain Amplifier 8-Bit Programmable Offset Adjustment CIS or CCD Compatibility Internal Clamp for CIS or CCD AC Coupled Configurations No Missing Codes at 10MHz ADC Clock 3.3V or 5V Operation & I/O Compatibility Serial Load Control Registers · · · Low Power CMOS: 200mW-typ Low Cost 20-Lead Packages USB Compliant APPLICATIONS · · · · · · · Color and Grayscale Flatbed Scanners Color and Grayscale Sheetfed Scanners Multifunction Peripherals Digital Color Copiers General Purpose CIS or CCD Imaging Low Cost Data Acquisition Simple and Direct Interface to Canon 600 DPI Sensors GENERAL DESCRIPTION The XRD9825 is a complete linear CIS or CCD sensor signal processor on a single monolithic chip. The XRD9825 includes a high speed 16-bit resolution ADC, a 6-bit Programmable Gain Amplifier with gain adjustment of 1 to 10, and 8-bit programmable input referred offset calibration range of 800mV. In the CCD configuration the input signal is AC coupled with an external capacitor. An internal clamp sets the black level. In the CIS configuration, the clamp switch can be disabled and the CIS output signal is DC coupled from the CIS sensor to the XRD9825. The CIS signal is level shifted to VRB in order to use the full range of the ADC. In the CIS configuration the input can also be AC coupled similar to the CCD configuration. This enables CIS signals with large black levels to be internally clamped to a DC reference equal to the black level. The DC reference is internally subtracted from the input signal. The CIS configuration can also be used in other applications that do not require CDS function, such as low cost data acquisition. ORDERING INFORMATION Package Type 20-Lead SOIC 20-Lead SSOP Temperature Range 0°C to +70°C 0°C to +70°C Part Number XRD9825ACD XRD9825ACU Rev. 1.00 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com XRD9825 * CIS REF Circuit VBG AVDD RED CLAMP * CIS REF Circuit Triple S/H & 3-1 MUX Power Down DVDD + BUFFER _ PGA VRT RL16-BIT ADC 16 DATA I/O PORT 8 DB7:0 VREF+ GRN BLU DC Reference VDCEXT INT/EXT_V DCREF CLP 6-BIT GAIN REGISTERS DC/AC R G B 6 G<5:0> V DCREF VRB DGND Power Down AVDD AGND 8-BIT DAC AGND 8 CIS/CCD 8-BIT OFFSET REGISTERS VRT CIS CCD R G B O<7:0> AGND SYNCH CLAMP TIMING & CONTROL LOGIC ADCCLK Note: * For Canon CIS Sensor Figure 1. Functional Block Diagram Rev. 1.00 2 XRD9825 PIN CONFIGURATION DVDD 1 DB0 DB1 DB2 DB3 DB4 DB5/SCLK DB6/SDATA DB7/LD 2 3 4 5 20 AVDD 19 RED 18 GRN 17 BLU 16 VDCEXT XRD9825ACD 6 7 8 9 15 VREF+ 14 AGND 13 SYNCH 12 CLAMP 11 ADCCLK DGND 10 20-Lead SOIC PIN DESCRIPTION Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol DVDD DB0 DB1 DB2 DB3 DB4 DB5/SCLK DB6/SDATA DB7/LD DGND ADCCLK CLAMP SYNCH AGND VREF+ VDCEXT BLU GRN RED AVDD Description Digital VDD (for Output Drivers) Data Output Bit 0 Data Output Bit 1 Data Output Bit 2 Data Output Bit 3 Data Output Bit 4 Data Output Bit 5 & Data Input SCLK Data Output Bit 6 & Data Input SDATA Data Output Bit 7 & LD Digital Ground (for Output Drivers) A/D Converter Clock Clamp and Video Sample Clock Start of New Line and Serial Data Input Control Analog Ground A/D Positive Reference for Decoupling Cap External DC Reference Blue Input Green Input Red Input Analog Power Supply Rev. 1.00 3 XRD9825 ELECTRICAL CHARACTERISTICS Test Conditions: AVDD=DVDD=5V, ADCCLK=12MHz, 50% Duty Cycle, TA=25°C unless otherwise specified. Symbol Parameter Min. Typ. Max. Unit Conditions Power Supplies AVDD DVDD IDD IDDPD RES Fs DNL VRB ∆VREF RL PGARES PGAGMIN PGAGMAX PGAGD VBLACK DACRES OFFMIN OFFMAX OFFMIN OFFMAX OFF∆ Analog Power Supply Digital I/O Power Supply Supply Current Power Down Power Supply Current Resolution Maximum Sampling Rate Differential Non-Linearity Bottom Reference Voltage Differential Reference Voltage (VRT - VRB) Ladder Resistance 300 600 780 Ω PGA & Offset DAC Specifications PGA Resolution Minimum Gain Maximum Gain Gain Adjustment Step Size Black Level Input Range Offset DAC Resolution Minimum Offset Adjustment Maximum Offset Adjustment Minimum Offset Adjustment Maximum Offset Adjustment Offset Adjustment Step Size -100 8 -250 +500 -450 +350 -200 +600 -400 +400 3.125 -150 +700 -350 +450 6 0.950 9.5 1.0 10.0 0.14 500 1.050 10.50 Bits V/V V/V V/V mV Bits mV mV mV mV mV Mode 111, D5=0 (Note 1) Mode 111, D5=0 Mode 111, D5=1 (Note 1) Mode 111, D5=1 DC Configuration 0.3 16 12 -0.7, +1.5 -0.8, +2.0 AVDD/10 0.67AV DD V V 3.0 3.0 25 3.3 3.3 40 5.5 5.5 60 50 V V mA µA Bits MSPS LSB ADCCLK = 10MHz ADCCLK = 12MHz (Note 2) DVDD < AVDD VDD=5V VDD=5V ADC Specifications Note 1: Note 2: The additional ±100 mV of adjustment with respect to the black level input range is needed to compensate for any additional offset introduced by the XRD9825 Buffer/PGA internally. It is not recommended to operate the part between 3.6V and 4.4V. Rev. 1.00 4 XRD9825 ELECTRICAL CHARACTERISTICS (CONT'D) Test Conditions: AVDD=DVDD=5V, ADCCLK=12MHz, 50% Duty Cycle, TA=25°C unless otherwise specified. Symbol IIL CIN VINPP Parameter Input Leakage Current Input Capacitance AC Input Voltage Range Min. Typ. Max. 100 10 0 AVDD-1.4 Unit nA pF V Conditions Buffer Specifications AC Input Voltage Range 0 ∆VREF V VIN DC Input Voltage Range -0.1 AVDD-1.4 V DC Input Voltage Range VDCEXT-0.1 VDCEXT+ ∆VREF V CIS AC; INT VDCREF Config Reg => XXX010XX Gain=1 (Note 1) CCD AC; INT VDCREF Config Reg => XXX011XX Gain=1 (Note 1) CIS DC; INT VDCREF Config Reg => XXX000XX Gain=1 (Note 2) CIS DC; EXT VDCREF Config Reg => XXX100XX Gain=1 (Note 3) VDCEXT+DVREF < AVDD CIS DC; EXT VDCREF Config Reg => XXX100XX fin=3MHz CIS (AC) Config CCD (AC) Config VDCEXT External DC Reference 0.3 AVDD/2 V VINBW VINCT VCLAMP RINT ROFF Input Bandwidth (small signal) Channel to Channel Crosstalk Clamp Voltage 3.5 Clamp Switch On Resistance Clamp Switch Off Resistance 10 10 -60 AGND VRT 100 -50 50 150 MHz dB mV V Ω MΩ Internal Clamp Specifications Note 1: VINPP is the signal swing before the external capacitor tied to the MUX inputs. Note 2: The -0.1V minimum is specified in order to accommodate black level signals lower than the external DC reference (clamp) voltage. Note 3: The VDCEXT-0.1V minimum is specified in order to accommodate black level signals lower than the external DC reference voltage. Rev. 1.00 5 XRD9825 ELECTRICAL CHARACTERISTICS (CONT'D) Test Conditions: AVDD=DVDD= 5V, ADCCLK=6MHz, 50% Duty Cycle, TA=25°C unless otherwise specified. Symbol SYSDNL SYSLIN SYSGE IRN Parameter System DNL System Linearity System Gain Error Input Referred Noise Input Referred Noise System Timing Specifications tcklw tckhw tckpd tsypw trars tclpw tsclkw tdz tds tdh tdl tap tdv tsa tlat tlat VIH VIL IIH IIL CIN ADCCLK Low Pulse Width ADCCLK High Pulse Width ADCCLK Period SYNCH Pulse Width Rising ADCCLK to rising SYNCH CLAMP Pulse Width SCLK Pulse Width LD Low to SCLK High Input Data Set-up Time Input Data Hold Time SCLK High to LD High Aperture Delay Output Data Valid SYNCH to ADCCLK Latency Latency Input High Voltage Input Low Voltage High Voltage Input Current Low Voltage Input Current Input Capacitance 5 5 10 AVDD-2.5 1 40 15 8 6 50 70 120 30 0 30 40 20 20 0 50 10 ns ns ns ns ns ns ns ns ns cycles pixels V V µA µA pF 3ch Pixel Md Config 00, 11 Config 01, 10 83 83 166 ns ns ns ns SYNCH must rise equal to or after ADCCLK, See Figure 18 Note 2 -5.0 1.5 0.5 Min. -1.0 Typ. ±0.5 ±6.0 +5.0 Max. +2.3 Unit LSB LSB % mVrms mVrms Gain=1 Gain=10 Conditions Note 1 System Specifications (MUX + Buffer + PGA + ADC) Write Timing Specifications ADC Digital Output Specifications Digital Input Specifications Note 1: Note 2: System performance is specified for typical digital system timing specifications. The actual minimum ‘tclpw’ is dependent on the external capacitor value, the CIS output impedance. During ‘clamp’ operation, sufficient time needs to be allowed for the external capacitor to charge up to the correct operating level. Refer to the description in Theory of Operation, CIS Config. Rev. 1.00 6 XRD9825 ELECTRICAL CHARACTERISTICS (CONT'D) Test Conditions: AVDD=DVDD=5V, ADCCLK=12MHz, 50% Duty Cycle, TA=25°C unless otherwise specified. Symbol Parameter Min. Typ. Max. Unit Conditions Digital Output Specifications VOH VOL IOZ COUT SR Output High Voltage Output Low Voltage Output High-Z Leakage Current Output Capacitance Slew Rate (10% to 90% DVDD) 2 -10 10 15 80 20 10 % DVDD % DVDD µA pF ns CL=10pF, DVDD=3.3V IL = 1mA IL = -1mA Rev. 1.00 7 XRD9825 THEORY OF OPERATION CIS Configuration (Contact Image Sensor) The XRD9825 has two configurations for CIS applications. Each configuration is set by the control registers accessed through the serial port. Mode 1. DC Coupled If the CIS does not have leading or trailing black pixels as shown in Figure 2, then DC couple the CIS output to the XRD9825 input. Optically Shielded Pixels Valid Pixels Figure 2. Typical Output CIS Mode Adjust the offset of the CIS (-100 mV to 500 mV) by setting the internal registers of the XRD9825 to set the black pixel value when the LEDs of the CIS are off. When the LEDs are on, use the XRD9825 Program- mable Gain to maximize the ADCs dynamic range. Figure 3, shows a typical application for a CIS with an offset of -100mV to 500mV. Rev. 1.00 8 XRD9825 XRD9825 VDD VRT C I S RED N/C N/C N/C M U X RL VRB Figure 3. Application with Offset in the Range (-100mv to 500mv) The input is added to VRB before the signal passes through the ADC. If the CIS output is zero, then the output of the ADC will be zero code. This enables the CIS to be referenced to the bottom ladder reference voltage to use the full range of the ADC. S