32 Macrocell CPLD

This product has been discontinued. Please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. www.DataSheet4U.com 0 APPLICATION NOTE R XCR3032: 32 Macrocell CPLD 0 14* DS038 (v1.3) October 9, 2000 Product Specification CMOS process technology and the patented full CMOS FZP design technique. For 5V applications, Xilinx also offers the high speed XCR5032 CPLD that offers pin-to-pin speeds of 6 ns. The Xilinx FZP CPLDs utilize the patented XPLA (eXtended Programmable Logic Array) architecture. The XPLA architecture combines the best features of both PLA and PAL type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLA structure in each logic block provides a fast 8 ns PAL path with five dedicated product terms per output. This PAL path is joined by an additional PLA structure that deploys a pool of 32 product terms to a fully programmable OR array that can allocate the PLA product terms to any output in the logic block. This combination allows logic to be allocated efficiently throughout the logic block and supports as many as 37 product terms on an output. The speed with which logic is allocated from the PLA array to an output is only 2.5 ns, regardless of the number of PLA product terms used, which results in worst case tPD's of only 10.5 ns from any pin to any other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density. The XCR3032 CPLDs are supported by industry standard CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor, Synopsys, Synario, Viewlogic, and Synplicity), using text (ABEL, VHDL, Verilog) and/or schematic entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on personal computer, Sparc, and HP platforms. Device fitting uses a Xilinx developed tool, XPLA Professional (available on the Xilinx web site). The XCR3032 CPLD is reprogrammable using industry standard device programmers from vendors such as Data I/O, BP Microsystems, SMS, and others. Features • • • • • • • • • • • • • • • • • • • Industry's first TotalCMOS™ PLD - both CMOS design and process technologies Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed High speed pin-to-pin delays of 8ns Ultra-low static power of less than 35 µA 100% routable with 100% utilization while all pins and all macrocells are fixed Deterministic timing model that is extremely simple to use Two clocks available Programmable clock polarity at every macrocell Support for asynchronous clocking Innovative XPLA™ architecture combines high speed with extreme flexibility 1000 erase/program cycles guaranteed 20 years data retention guaranteed Logic expandable to 37 product terms PCI compliant Advanced 0.5µ E2CMOS process Security bit prevents unauthorized access Design entry and verification using industry standard and Xilinx CAE tools Reprogrammable using industry standard device programmers Innovative Control Term structure provides either sum terms or product terms in each logic block for: - Programmable 3-state buffer - Asynchronous macrocell register preset/reset Programmable global 3-state pin facilitates ‘bed of nails' testing without using logic resources Available in both PLCC and VQFP packages • • Description The XCR3032 CPLD (Complex Programmable Logic Device) is the first in a family of CoolRunner® CPLDs from Xilinx. These devices combine high speed and zero power in a 32 macrocell CPLD. With the FZP design technique, the XCR3032 offers true pin-to-pin speeds of 8 ns, while simultaneously delivering power that is less than 35 µA at standby without the need for “turbo bits” or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD. These devices are the first TotalCMOS PLDs, as they use both a DS038 (v1.3) October 9, 2000 www.xilinx.com 1-800-255-7778 1 This product has been discontinued. Please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. R XCR3032: 32 Macrocell CPLD XPLA Architecture Figure 1 shows a high level block diagram of a 32 macrocell device implementing the XPLA architecture. The XPLA architecture consists of logic blocks that are interconnected by a Zero-power Interconnect Array (ZIA). The ZIA is a virtual crosspoint switch. Each logic block is essentially a 36V16 device with 36 inputs from the ZIA and 16 macrocells. Each logic block also provides 32 ZIA feedback paths from the macrocells and I/O pins. From this point of view, this architecture looks like many other CPLD architectures. What makes the CoolRunner family unique is what is inside each logic block and the design technique used to implement these logic blocks. The contents of the logic block will be described next. configured as either SUM or PRODUCT terms, and are used to control the preset/reset and output enables of the 16 macrocells’ flip-flops. The PAL array consists of a programmable AND array with a fixed OR array, while the PLA array consists of a programmable AND array with a programmable OR array. The PAL array provides a high speed path through the array, while the PLA array provides increased product term density. Each macrocell has five dedicated product terms from the PAL array. The pin-to-pin tPD of the XCR3032 device through the PAL array is 8 ns. If a macrocell needs more than five product terms, it simply gets the additional product terms from the PLA array. The PLA array consists of 32 product terms, which are available for use by all 16 macrocells. The additional propagation delay incurred by a macrocell using one or all 32 PLA product terms is just 2.5 ns. So the total pin-to-pin tPD for the XCR3032 using six to 37 product terms is 10.5 ns (8 ns for the PAL + 2.5 ns for the PLA). Logic Block Architecture Figure 3 illustrates the logic block architecture. Each logic block contains control terms, a PAL array, a PLA array, and 16 macrocells. The six control terms can individually be MC1 MC2 I/O MC16 16 16 ZIA MC1 MC2 I/O MC16 16 16 16 16 LOGIC BLOCK 36 36 LOGIC BLOCK 16 16 LOGIC BLOCK 36 36 LOGIC BLOCK MC1 MC2 I/O MC16 MC1 MC2 I/O MC16 SP00439 Figure 1: Xilinx XPLA CPLD Architecture DS038 (v1.3) October 9, 2000 www.xilinx.com 1-800-255-7778 2 This product has been discontinued. Please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. R XCR3032: 32 Macrocell CPLD 36 ZIA INPUTS CONTROL 5 6 PAL ARRAY PLA ARRAY (32) SP00435A Figure 2: Xilinx XPLA Logic block Architecture 3 www.xilinx.com 1-800-255-7778 DS038 (v1.3) October 9, 2000 TO 16 MACROCELLS This product has been discontinued. Please see www.xilinx.com/partinfo/notify/pdn0007.htm for details. R XCR3032: 32 Macrocell CPLD Macrocell Architecture Figure 3 shows the architecture of the macrocell used in the CoolRunner family. The macrocell consists of a flip-flop that can be configured as either a D- or T-type. A D-type flip-flop is generally more useful for implementing state machines and data buffering. A T-type flip-flop is generally more useful in implementing counters. All CoolRunner™ family members provide both synchronous and asynchronous clocking and provide the ability to clock off either the falling or rising edges of these clocks. These devices are designed such that the skew between the rising and falling edges of a clock are minimized for clocking integrity. There are two clocks (CLK0 and CLK1) available on the XCR3032 device. Clock 0 (CLK0) is designated as the "synchronous" clock and must be driven by an external source. Clock 1 (CLK1) can either be used as a synchronous clock (driven by an external source) or as an asynchronous clock (driven by a macrocell equation). The timing for asynchronous clocks is different in that the tCO time is extended by the amount of time that it takes for the signal to propagate through the array and reach the clock network, and the tSU time is reduced. Two of the control terms (CT0 and CT1) are used to control the Preset/Reset of the macrocell's flip-flop. The Preset/Reset feature for each macrocell can also be disabled. Note that the Power-on Reset leaves all macrocells in the "zero" state when power is properly applied. The other four control terms (CT2-CT5) can be used to control the Output Enable of the macrocell's output buffers. The reason there are as many control terms dedicated for the Output Enable of the macrocell is to insure that all CoolRunner devices are PCI compliant. The macrocell's output buffers can also be always enabled or disabled. All CoolRunner devices also provide a Global 3-state (GTS) pin, which, when enabled and pulled Low, will 3-state all the outputs of the device. This pin is provided to support "In-Circuit Testing" or "Bed-of-Nails” testing. There are two feedback paths to the ZIA: one from the macrocell, and one from the I/O pin. The ZIA feedback path before the output buffer is the macrocell feedback path, while the ZIA feedback path after the output buffer is the I/O pin ZIA path. When the macrocell is used as an output, the output buffer is enabled, and the macrocell feedback path can be used to feedback the logic implemented in the macrocell. When the I/O pin is used as an input, the output buffer will be 3-stated and the input signal will be fed into the ZIA via the I/O feedback path, and the logic implemented in the buried macrocell can be fed back to the ZIA via the macrocell feedback path. It should be noted that unused inputs or I/Os should be properly terminated. Terminations The CoolRunner XCR3032 CPLDs are TotalCMOS devices. As with other CMOS